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USB low-full-high speed peripherals Forum Discussions

Anonymous
Not applicable

Hello everyone!

i am trying to transfer data from spartan 6 to pc and vice versa via fx2lp ( cy7c68013a). i want to use slave fifo and i have made fifoadr[1:0]=1, but i dont know how to make ifcfg[1:0]=1. can anyone explain me basic flow of interfacing of fx2 with fpga and how to configure this things?

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1 Solution
Sananya_14
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750 replies posted 500 replies posted 250 solutions authored

Hello,

Please check the following-

1. Please set REVCTL as 0x00 and switch EP8FIFOCFG from 0x00 to 0x10 to arm it as it is an OUT endpoint.

2. Please configure Endpoint 8 as double buffered. You can refer to the TRM for endpoint buffering details in Section 1.17.

3. Please ensure that the external clock is present from the FPGA before configuring IFCONFIG as external source.

Best Regards,

Sananya

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Sananya_14
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750 replies posted 500 replies posted 250 solutions authored

Hello,

IFCONFIG is a register which puts FX2LP in various modes and for slave FIFO interface you can set it for e.g. as 0xE3 which configures it in slave FIFO mode with internal IFCLK, 48 MHz . Please refer to the Technical Reference Manual at C:\Cypress\USB\CY3684_EZ-USB_FX2LP_DVK\1.1\Documentation\EZ-USB(R) Technical Reference Manual.pdf for more register details.You can refer to the Application Note on Slave FIFO interface for interfacing with FPGA and also find an example firmware attached. 

Best Regards,

Sananya

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Anonymous
Not applicable

Hi Sananya,

i have created hex file of updated .c code in which i have selected async mode. FIFOADR i have given already as 11 ( fifoadr[1] and fifoadr[0] both 1). EP8FIFOCFG= 0x00 ( 8 bit data mode) , i had download hex file into chip, still i am unable to transfer the data. What can be went wrong? Am i missing something here?

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Sananya_14
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750 replies posted 500 replies posted 250 solutions authored

Hello,

Please make sure that Endpoint 8 is configured properly using EP8CFG register and FIFO 8 is reset in TD_Init().

Since you are putting the FIFO in manual mode by setting EP8FIFOCFG as 0x00, you need to manually commit the data to be either read by  the host from the slave FIFO interface or written to the slave FIFO interface when data is sent from the host. You can set it to auto mode if you want the data to be automatically committed to host or FPGA side. If you still face any errors, please share your firmware with us.

Best Regards,

Sananya

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Anonymous
Not applicable

Hello,

My EP8CFG reg value is 0xE0 ..... here's my TD_Init()

I have made it to Auto mode.

EP8 - IN

EP6 - OUT

Is this config is right?

-------------------------------------------------------------------------------------------------------

void TD_Init(void)             // Called once at startup

{

  

  

// set the CPU clock to 48MHz

     CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;

   // set the slave FIFO interface to 48MHz

     IFCONFIG |= 0x0B; // IFCONFIG |= 0x40;

     SYNCDELAY;

     REVCTL = 0x03;

     SYNCDELAY;

FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions

SYNCDELAY;       // see TRM section 15.14

FIFORESET = 0x06; // reset, FIFO 6

SYNCDELAY;

FIFORESET = 0x08; // reset, FIFO 8

SYNCDELAY; //

FIFORESET = 0x00; // deactivate NAK-ALL

SYNCDELAY;

  EP1OUTCFG = 0xA0;    // Configure EP1OUT as BULK EP

SYNCDELAY;

     EP1INCFG = 0xB0;     // Configure EP1IN as BULK IN EP

     SYNCDELAY;                    // see TRM section 15.14

     EP2CFG = 0x7F;       // Invalid EP

     SYNCDELAY;                   

     EP4CFG = 0x7F;      // Invalid EP

     SYNCDELAY;

                 

     EP6CFG =    0XA0;           // 0x7F;   

     SYNCDELAY;                 

     EP8CFG = 0xE0;      // Configure EP8 as BULK IN EP

     SYNCDELAY;   

 

     EP6FIFOCFG = 0x10;

     SYNCDELAY;

     EP8FIFOCFG = 0x08;  // Configure EP8 FIFO in 8-bit Auto (first it was Manual) Commit mode 0x00

     SYNCDELAY;  

     T2CON  = 0x34;     

EPIE |= bmBIT3 ;              // Enable EP1 OUT Endpoint interrupts

  

  AUTOPTRSETUP |= 0x01;         // enable dual autopointer feature

  Rwuen = TRUE;                 // Enable remote-wakeup

  EP1OUTBC = 0x04;

ES0 = 1; /* enable serial interrupts */

PS0 = 0; /* set serial interrupts to low priority */

TI = 1; /* clear transmit interrupt */

RI = 0; /* clear receiver interrupt */

EA = 1; /* Enable Interrupts */

 

     Serial0Init();      // Initialize the Serial Port 0 for the Communication SCO

}

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Anonymous
Not applicable

Hello,

This is my updated code Elements. (CY7C68013A)

EP8- OUT FIFO

EP6- IN FIFO

PINFLAGSAB - E0 ( FOR EP6 FULL FLAG)

PINFLAGSCD - 0B (FOR EP8 EMPTY FLAG)

PORTACFG- 0X40;

PA7 to GND

My code:---------------------------------------------------------------------------------------------------------------------------------------------------------

void TD_Init(void)             // Called once at startup

{

  

  

// set the CPU clock to 48MHz

     CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;

   // set the slave FIFO interface to 48MHz

     IFCONFIG |= 0x0B; // IFCONFIG |= 0x40;

     SYNCDELAY;

     REVCTL = 0x03;

     SYNCDELAY;

////-------------    

     FIFOPINPOLAR = 0x20; // PKTEND IS HIGH

     SYNCDELAY;

     PINFLAGSAB = 0xE0;

     SYNCDELAY;

     PINFLAGSCD = 0x0B;

     SYNCDELAY;

////---------------

FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions

SYNCDELAY;       // see TRM section 15.14

FIFORESET = 0x06; // reset, FIFO 6

    SYNCDELAY; 

FIFORESET = 0x08; // reset, FIFO 8

SYNCDELAY; //

FIFORESET = 0x00; // deactivate NAK-ALL

SYNCDELAY;

  EP1OUTCFG = 0xA0;    // Configure EP1OUT as BULK EP

SYNCDELAY;

     EP1INCFG = 0xA0;     // Configure EP1IN as BULK IN EP

     SYNCDELAY;                    // see TRM section 15.14

     EP2CFG = 0x7F;       // Invalid EP

     SYNCDELAY;                   

     EP4CFG = 0x7F;      // Invalid EP

     SYNCDELAY;                   

     EP6CFG = 0xE0;        //     first it was 0x7F;     

     SYNCDELAY;                  

     EP8CFG = 0xA0;      // Configure EP8 as BULK IN EP - FOR READ 

     SYNCDELAY;    

 

 

     EP6FIFOCFG = 0x00; 

     SYNCDELAY;                   

     EP6FIFOCFG = 0x08;

     SYNCDELAY;

     EP8FIFOCFG = 0x10;     // Configure EP8 FIFO in 8-bit Auto (first it was Manual) Commit mode 0x00

     SYNCDELAY; 

     PORTACFG =  0x40;

    SYNCDELAY;

     T2CON  = 0x34;     

EPIE |= bmBIT3 ;              // Enable EP1 OUT Endpoint interrupts

  

  AUTOPTRSETUP |= 0x01;         // enable dual autopointer feature

  Rwuen = TRUE;                 // Enable remote-wakeup

  EP1OUTBC = 0x04;

ES0 = 1; /* enable serial interrupts */

PS0 = 0; /* set serial interrupts to low priority */

TI = 1; /* clear transmit interrupt */

RI = 0; /* clear receiver interrupt */

EA = 1; /* Enable Interrupts */

 

     Serial0Init();      // Initialize the Serial Port 0 for the Communication SCO

}

------------------------------------------------------------------------------------------------------------------------------------------------------------

still i am not receiving data from out fifo (to fpga).

can you guide me through this problem?

--

Regards,

Avinash

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Sananya_14
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hello,

Please check the following-

1. Please set REVCTL as 0x00 and switch EP8FIFOCFG from 0x00 to 0x10 to arm it as it is an OUT endpoint.

2. Please configure Endpoint 8 as double buffered. You can refer to the TRM for endpoint buffering details in Section 1.17.

3. Please ensure that the external clock is present from the FPGA before configuring IFCONFIG as external source.

Best Regards,

Sananya