USB low-full-high speed peripherals Forum Discussions

Hi,

I've a problem  with a special laptop and my cy7c68013A device (driver version 3.4.7).
After booting the Laptop my device is running fine (I can communicate via  CyUSB.dll).
But after a random time (up to hours) this connection breaks and my device will no longer be enlisted in  
CyUSB.USBDeviceList(CyUSB.CyConst.DEVICES_CYUSB). It also is missing in the CyConsole app. But it is enlisted in the device manager!

After cycling the USB cable, the device reappears in my application as well as in the CyConsole app.

(Un)fortunatly this only happens with one single laptop. Any ideas what is going on? 

Best
Marcus

I have a CY7C68013A-based design that I am supporting.

The design uses the GPIF to interface with an FPGA. We are using the IFCLK in internal mode (48MHz), undriven. The FPGA is clocked by CLKOUT (also 48MHz). I am trying to understand whether there is a known timing relationship between these 2 clocks, or whether I need to treat the GPIF as asynchronous to CLKOUT.  I have not found any reference to a relationship between these 2 clocks in any of the documentation that I have.

Hello,

This IC is used as a master to transmit data to a slave microcontroller via SPI communication.
SPI communication is used to send data to the slave microcontrollers.
However, the output time of this IC is less than half of the clock time.
It is difficult to satisfy the AC timing (hold time) between the slave microcontroller and the receiver microcontroller.
We are having a hard time satisfying the AC timing (hold time) between the slave microcontroller and the receiver microcontroller.

Q1)

In the data sheet of this IC, "Figure 1.SPI Master Timing" in the datasheet of this IC.
In the time chart of SPI Master Timing for CPHA = 0, MOSI(output) is output on the falling edge of SCK and
The output ends at the rising edge of SCK.
Therefore, the hold time is 0ns (THMO = 0ns).
Is this timing correct for data output?

Is data not output during one cycle from the falling edge of SCK to the falling edge of the next cycle?

(although in slave mode, one cycle of data retention is requested from the other side).

Q2)

Regarding question 1, if there is no mistake in the timing on the data sheet, the actual measurement of the data appears to show that the data changes with each falling edge of SCK.(every cycle).

This means that if the output is OFF at half-clock on SCK, the remaining half-wave is The high input impedance of the microcontroller on the receiver Is it correct to think that the potential is held by the capacitive component of the circuit? Is this correct?

Q3)

In relation to question 2 above, even after the output gate is turned off, does the output have an internal structure that keeps the potential for a while?
(How many pF is the output capacitance of this IC terminal?

Regards.

We used this CY7C65630-56LFXA chip on our equipment. On each unit, we have two chips to control 6 SD cards. While on Win7 OS, we have no problems to harvest the data on all 6 SD cards. After switching to Win10 OS, we can only see one SD card each time. We searched online and tried many solutions, but none of them helped us. Is this a driver issue? Any suggestion how to solve this problem?

One engineer said we can replace this chip with a new one, which has the same pins and works on Win10 and Win11. We don't need to modify the design and other parts. Do you have a recommended chip? 

Thank you.  

HI,

I use USB Control Center to wite to EEPROM as shown in Figure 7-17 in CY3674/CY3684 EZ-USB Development Kit User Guide. But I found I can not write an image file larger than 512 bytes. Could you help? Thanks.

Regards

yakgg

Hi, 

We are validating RTS/CTS flow control of UART vendor mode on CYUSB236 EVK by sending a 7MB text file from SCB0 to SCB1. With referring to Cypress USB API document, we develop a program via Cypress Linux library to send, receive data, enable RTS/CTS flow control and register CTS notification callback function.

With RTS/CTS flow control enabled on both UART ports, the receiver(SCB1) showed some packets loss as transmitter(SCB0) just continuously sent data without knowing how to check CTS status.

We can’t find any Cypress document or sample codes of handling CTS via Cypress library on CYUSB236 or CY7C65215 website. 

Could you provide document or sample codes of implementing RTS/CTS flow control correctly via Cypress library to prevent packets loss on receiver ?

Best Regards,

Justy Huang