USB low-full-high speed peripherals Forum Discussions
How to disarm previously armed in EP1IN?
Hi
I am interested in using the EZ USB chips for a new design and would like some help choosing the best part that has software example to prove concept. These are the requirements:
- USB 2.0 device (USB 3.0 not available for this application) on Windows platforms
- Supporting OV5640 (or equally similar image sensor) running in 8 bit parallel mode output is YUV and MJPEG
- Video capture using UVC drivers (ie. looks like a webcam to PC requiring no drivers to be written)
- Capture of images of at least 1M pixels (at least 1280x1024 SXGA resolution at 15 fps min). For this, compression is required (if I am not mistaken) and the OV5640 supports MJPEG.
- Application is cost sensitive so I would ideally like to go with the EZUSB 2 devices as opposed to the newer EZ USB 3 devices (unless the EZUSB 2 devices are to be obsoleted in the next 5 years)
- There is a space constraint where the PCB width should not exceed 8mm so the 56 pin BGA EZ USB 2 devices are very attractive
Can you please recommended a suitable part that has a reference design that I can use/adapt to achieve a proof of concept.
Thanks in advance
Show LessProbably answering the question myself, the TRM states that the aadj=1 will check only 1024byte commited buffers but I was wondering if it should work also on 512byte packets /fifo buffers for IN(2) endpoints. It doesn't seem to work with me so I was wondering if it is suposed to or if by design it doesn't, then, is there any sample on how to do the pid sequencing in the firmware? I need the quad buffering and (512*3)*8
Thank you in advance.
Show Lesshi Cypress:
The problem with cy7c68013a-56ltxc is that the host computer needs to send 512Byte or integer multiple data to receive it. If the data sent is less than 512Byte, it cannot be received. In the relevant protocol of USB, it should be necessary to send relevant operation instructions to achieve non-512byte acceptance. The customer needs to know how to operate. Whether there are relevant operation documents;
Show LessHello,
We designed a device that uses Cypress CY7C68013 chip in order to initiate USB2 high speed communication (30MB/s throughput).
We want our users to be able to use the device with Windows 10 64 bit and 32 bit operating systems.
The installation should be plug-and-play, so as the user connects the device to the PC, Windows 10 should recognize it (using it's VID and PID numbers) and provide the drivers from Windows Update.
The driver that Cypress provides (CyUsb3) works for our device and the only change we have to make is to change the VID and PID numbers in the INF file.
As far as we understand, when the INF file is changed, the driver files should be re-signed using EV code signing certificate.
I wonder how does the driver-reselling service works and how can it help us?
We have the following questions:
1. Do we have to provide you the modified INF file?
2. Do you sign the driver files (SYS, INF, etc.) and create a new CAT file as part of the service?
3. Do we have to provide the EV code signing certificate for the signing process?
4. Does Cypress send the signed drivers for WHQL certification? Who does this part?
5. How can we apply to the sevice?
Thanks.
Show LessI assume that SIE of FX2LP responds immediately to EP1IN bulk transaction without NACK one or two times soon after "SET_FEATURE(to endpoint81) REQUEST" although firmware does not arm the EP1IN yet.
EP1IN is armed in accordance with timer2 expilation by polling TF2. SIE seems to ignore these intervals. Is my opinion right ?
Show LessHello,
I am considering using FX3 as a bridge between USB and FPGA.
It would be mainly used to pass data from USB to application via FX3 at maximum BW (low traffic in other direction).
My project is at board design level.
Looking at documentation and tools, it looks like 32-bit synchronous FIFO Slavemode @ 100 MHz would be OK for me.
All implementations I found describe an interface where FPGA is master of the clock.
I would like to keep the ability to have FX3 driving this clock (still using maximum frequency, ie 100 MHz).
Example design provided in GPIF designer does not allow to modify clock direction.
Is there a simple solution to do so ? Or should I redesign everything (GPIF interface definition, state machine, FX3 firmware...)
Are there side effects using such a configuration ?
Thanks for your help
Christophe
Show LessWhat modes are cy7c65215 jtag's output pins: Open-drain or push-pull? Are they configurable?
Also, should we have a pull-up resistor for TDO (jtag master's input pin)?
SCB1 pins:
TDO // jtag master input pin
TDI // jtag master output pin
TMS
TCK
TRST
Thanks,
Show LessHello,
I work as a computer technician for a french hospital and I'm searching for a driver.
After HDD crash, I reinstalled a computer who is connected to an obscure medical peripheral.
I couldn't find any source file for the driver...
Maybe someone at Cypress could help ? The device vendor ID match "Cypress Semiconductor Corp." when I search on the internet.
Device Vendor : VID_04B4
Device ID : PID_CC04
Device description : CTCUSB
Before HDD crash, operating system was Windows XP x64
Thanks,
Pierre
Show LessHi Service desk,
1) What are the functional differences between issuing hard reset to RESET_N pin Vs soft reset using USB->Reset().
2) Also, How to apply "CPU only Reset" or "Whole device reset" using the soft reset mechanism?
Thanks,
Trinath
Show Less