Hi,

The FX2LP18 is definitiely choosen for our board.

I read the AN15456 application note to write my specifications.

Is there any others recommandation for FX2LP18 with 1.8 VIO ?

Concerning the 1.8V LDO which one is recommanded ?

Is there any schematics to be shared ?

Thanks.

I have binary images for these devices that I wish to upload

I would best describe the Cypress tools as a joke, no command line to do it and I cannot get the control center to do it
I was considering these for a unit I am currently designing but no more

The lack of clear instruction and effective, easy to use tools is a deal breaker for me

How do I achieve the goal both on the test bench and in production?

Hello,

I wanted to configure my CY7C65215 with SCB0 being a I2C master, but I just wanted to use the Cypress Vid/Pid.  So, I configured the device as below.  Unfortunately, that doesn't load the vendor driver correctly as it is not in the .inf that way. 

I would like to re-configure the part, but I don't see to be able to get back to manufacturing mode.   These are the HW IDs I have in Device Manager:

I followed the instructions here: Cypress USB-Serial with Custom VID/PID and Manufacturing Interface Disabled - KBA222695   (Update driver, CypressSerial.inf... -> Usb-Serial Composite Device; then select the new device that has the _MI on it and select the vendor driver....   But it doesn't show up in the config utility. 

Am I doing somethign wrong?  Should I be able to re-configure this Cypress part after configuring as above (Manufacturing interface disabled)?  Is there a way for me to get back to that state?

Thanks!

- Gary

Interfacing FX2LP™ with Image Sensor – KBA95736

For above document reference May I know which Image sensor used with FX2LP?

May I know few details about Interconnect board?

Is Aptina Interconnect board  https://www.cypress.com/documentation/development-kitsboards/cyusb3acc-004-aptina-image-sensor-interconnect-board-ez-usb…

suitable for any Image sensor or only for particular image sensor?

Thanks,

Esakki

Hello, dear

TS Data -> CY7c68013->PC

recently,i am doing a job which mpeg2-Ts stream Transferred to a computer.i used cy7c68013a-56 chip,endpoint2 bulk in 4xbuffer.Frimware，i reference to http://www.cypress.com/?rID=39714

My problem,

in most case, FIFO buffer is filled with zero (0x00,0x00,0x00....) instead of real ts data.

1 out of 100 test case,  FIFO buffer is filled with valid packet (0x47,....).

Here's what I tried so far.

I tried both Free Running MPEG CLK & Gated MPEG CLK but it has same problem.

SLRD#/SLOE#/ PKTEND  ->Pulled High

SLCS#/FIFOADR [0]/FIFOADR [1] -> Pulled Low

I tried PKTEND Pulled Low

tried window application on sync mode & async mode, but same problem. (xferData, beginXferData)

tried cypress streamer tool -> it has same symptom (mostly zero packet, randomly valid packet). tried with fx2 & fx3 window application. same problem.

here's my firmware code. could you pls suggest where to check, or fix?

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

CPUCS = 0x10;

SYNCDELAY;

#ifdef _USE_INTERNAL_IF

IFCONFIG = 0xCB; // use IFCLK pin driven by external logic (5MHz to 48MHz)  Inverted  : 0x13 Async

#else

IFCONFIG = 0x03; // use IFCLK pin driven by internal logic (5MHz to 48MHz) sync

#endif

EP2CFG = 0xE0; // EP2 is DIR=IN, TYPE=BULK,SIZE=512,BUF x4 
SYNCDELAY;
EP4CFG = 0x00; // clear valid bit
SYNCDELAY; //
EP6CFG = 0x00;  // clear valid bit
SYNCDELAY; //
EP8CFG = 0x00; // clear valid bit
SYNCDELAY;

// Clear out any committed packets
    FIFORESET = 0x80; //activate NAK-ALL to avoid race conditions
    SYNCDELAY;
    FIFORESET = 0x82;
    SYNCDELAY;
    FIFORESET = 0x84;
    SYNCDELAY;
    FIFORESET = 0x86;
    SYNCDELAY;
    FIFORESET = 0x88;
    SYNCDELAY;
    FIFORESET = 0x00;  //deactivate NAK-ALL
    SYNCDELAY;

EP2FIFOCFG = 0x08; // EP2 is INFM = 0, AUTOOUT=0, AUTOIN=1, ZEROLEN=0, WORDWIDE=0  0x0C : Auto In = 1 , ZeroLen = 1
SYNCDELAY;

FIFOPINPOLAR = 0x04; // set all slave FIFO interface pins as active low, 0x04 active hi  need to check...
SYNCDELAY;
EP2AUTOINLENH = 0x02; // EZ-USB automatically commits data in 512-byte chunks
SYNCDELAY;
EP2AUTOINLENL = 0x00;
SYNCDELAY;

PORTACFG = 0x00;  // used PA7/FLAGD as a port pin, not as a FIFO flag  #SLCS = 0x80
SYNCDELAY;

PINFLAGSAB = 0x00;  // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]
SYNCDELAY;    // FLAGB as full flag, as pointed to by FIFOADR[1:0]
PINFLAGSCD = 0x00;  // FLAGC as empty flag, as pointed to by FIFOADR[1:0]
SYNCDELAY;     // won't generally need FLAGD

EP2FIFOPFH = 0x80; // you can define the programmable flag (FLAGA)
SYNCDELAY; // to be active at the level you wish
EP2FIFOPFL = 0x00;
SYNCDELAY;

REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1  by TRM Doc 9.3.9 Auto In/Out
SYNCDELAY;

IOA = 0; //

// enable dual autopointer feature
//AUTOPTRSETUP |= 0x01;

EP0BCH = 0;
EP0BCL = 64;

// We want to get SOF interrupts
USBIE |= bmSOF;

  Rwuen = TRUE;

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

I'm looking forward answer.

Thanks.

OK.

After FPGA loading we use the SLAVE FIFO interface. The FPGA is the MASTER.

Behind the SLAVE FIFO there is a Finite STate Machine. This FSM wait for a COMMAND from HOST. This COMMAND is made of several bytes. It is analyzed  Then if is a READ COMMAND, the FPGA writes the ANSWER into the BUFFER and indicates to the FX2 that is must send DATA.

In your previous answer, I've not understood exactly HOW the FPGA can inform the HOST PC that is has DATA to send ?

Could you precise this ?

What we need to do in terms of PC Software ? firmware ? And FPGA side ?

Goel is to avoid doing USB POLLING like today, with a READ COMMAND.

Thanks.

The instructions show a picture, it looks like pin 2 to 5 creates loop back.

Does anyone know for sure, there is just a photo and no pin numbers are

mentioned?  Don't want to damage my prototype board.

Thanks!

Hi,

We already use the GPIF solution for FPGA downloading.

We are studying an enhancement of the GPIF to work in // by 16.

The firmware has been modified accordingly.

The Bistream Size can be more or less 64 Mo. (XILINX UltraScale+ VU7P).

I've update the Visual C# 2008 project to be able to support the .BIN file of 64Mo.

The file_buffer point to the .BIN file

The file_bytes is the size of the .BIN : 53439904

As soon as i execute this  :

success = myDevice.BulkOutEndPt.XferData(ref file_buffer, ref file_bytes);

the file_bytes return Something that is not the file_bytes => All data have not been sent through the BulkOut. Why ? This is my problem ....

I tried with the original CyDLL.dll from the AN (from 2009) and with the one form 2014.

With the DLL from 2014, the file_bytes is even set to 0 !!! 0 bytes has been sent with the 64Mo file ...

Is there any limitation in terms of size using the BulkOutEndPt.XferData ?

If i use a smaller .BIN file it works.

Thanks for your help.