USB low-full-high speed peripherals Forum Discussions

hi,

New to Fx2. How the FX2 native vendor command 0xA0 works and where is it stored?. How is it invoked?.  what is the I2C address of the (small) eeprom that stores the VidPid?.  

Hi, I need to know few details for the part CY7C65215A-32LTXI.

1.Current status of the part.

2.If active, then how long it will be supported?

3.Is there any plan for EOL for this part?

4.Can you provide me ROHS document for this part?

Consider this as priority and respond me as soon as possible.

Hi,

I am using CY3689 DK for displaying video / image on VLC or MPC-HC player.

I have taken "https://community.cypress.com/t5/Knowledge-Base-Articles/USB2-0-Camera-Interface-Using-FX2LP-and-Lattice-CrossLink-FPGA/ta-p/248972" example as a reference. Changed endpoint buffers in Slave FIFO implementation part of example code. But I am not seeing any display on VLC or MPC-HC player.

I am also trying to analyze Wireshark packet but not able to do so. Please help to suggest what might be wrong here.
I will attach here the Wireshark capture data for your reference.

Hi,

I have connected the CYUSBS234 with my PC.  I didn't see the "Cypress usb console windows driver" and "USB serial port(COM4)", only have the "USB-SERIAL(SINGLE CHANNEL)Vendor 1" and "USB-SERIAL(SINGLE CHANNEL)Vendor MFG".

I have installed " Cypress USB-serial Driver" and "cyusb3" and "cyusbserial".  And I didn't see the win10 driver in the bin folder.

I'm using Win10。

Thanks, 

Hi,

I would like to know if there is a standard firmware with both I2C , GPIF interface and configuration utility available for EZ-USB® FX2LP CY7C68013A  controller.

We have used USB-Serial Bridge CY7C65215A controller. It is much simpler to develop application with CY7C65215A by just configuring settings with the help of USB-Serial Configuration Utility.

I would like to know if we can have similar functionality available with EZ-USB® FX2LP CY7C68013A  chip. 

The Crystal requirements for the FX2LP are clearly stated in the datasheet and several article on the community support site.

• 24 MHz +/- 100 ppm
• Parallel resonant
• Fundamental mode
• 500 μW drive level
• 12 pF (5% tolerance) load ca

Does Cypress have any recommendations for using a current limiting resistor to reduce the 500uW drive level requirement?

The card was not able to be read after changed the VID and PID settings using the "USB Serial Configuration Utility"  as below;

from =  \VID_04B4&PID_0003&MI_00

to =  \VID_04B2&PID_0002&MI_00

Please advise how to revert back these and bring back the card alive.

Any methods to master reset?

Thanks!

Hello,

We have chosen FX2LP 56 pin package USB Controller and for the slave FIFO interface we have followed AN61345 design guide but in the design guide PC0 and PC1 signals are there but whichever package we have selected in that PC0 and PC1 signals are not there. So if we want to use PC0 and PC1 signals then how can we use?

Regards,

Aditya Upadhyay

Hi

I am using CY3689 DK with Microsemi FPGA with slave FIFO implementation.

When I am sending a fixed data 0xF124 (16 bit data) from FPGA to FX2LP device, I am able to receive all data in USB control center properly.

But when I am trying to change my data, I am  getting wrong data on USB CS tool. I tried to send CCCC on first clock transaction and DDDD on next clock transaction and so on. But I am getting the following(attached image for your reference).

I am not sure why I am only facing this issue when I am changing my data on data bus. With fixed data it works fine. Please suggest the possible issue that might be the cause.

My expected output here is CCCC DDDD CCCC DDDD .......