Hi,   

is it possible to protect an USB HUB 

so even if there are every second an ESD Peak 4kV

to GND or the Shield of the cable to communicate without interruption

with 12mbits fullspeed.

Is there a driver or protokoll available which granty, that no protocol will be lost?

Hi,

My question could sound strange but i'm wondering if it is possible to add Virtual Com Port functionnality onto our existing FX2LP18 Firmware / Host Software based onto CyUSB3.inf (that used GPIF and Slave FIFO ).

I could use the I2C channel to "emulate" UART.

Regards.

We are planning to use the CY7C65213 USB chip in some of our hardware and program our own USB VID/PID.  I have seen on this forum that you can simply modify the cypress .inf file to add the custom VID/PID and then manually update the driver.  However, doing so invalidates the Windows device signing and prompts the user with a security message.  We need to be able to install the updated driver directly from our installer, without user prompt and have it recognized as a signed Windows driver.

What is the process to get an officially signed Windows (and MacOS Catalina and older and Big Sur and newer) driver package that uses VID/PID's?  Can Cypress handle this for us, or do we need to build and submit our own custom driver?  If the latter, what is that process?

Hi everyone,

I just downloaded AN64020 project  on Cypress page and did the following instruction in document. After installing driver for my device, I uploaded firmware to my device CY7C68013A-56PVXC in USB Control Centre and then this software showed new name for my device called "Mouse". Unfortunately, I typed F1, F2, F3, F4 following the document but nothing happened. Anyone can help me!

This below is link and images from my PC:

https://www.cypress.com/documentation/application-notes/an64020-creating-fx1fx2lp-composite-hid-device

Do you have a thorough analysis of the Cypress firmware architecture and USB enumeration related documents?

Hi,

We're using your CY7C65215 part to go from USB to I2C in master mode. We have found a strange behaviour on a read from from your device on the bus. On the SDA line, the CY7C65215 is pulling unexpectedly the bus low on a falling edge of the clock making the voltage dropping lower than -500mV with is the limit of the input buffer of the other component on the bus (see screen capture, blue signal). How come the CY7C65215 is pulling the bus low?

Thanks in advance,

Kind regards,

Xavier

Why I have changed the type to ISO, but still BULK type after downloading the firmware ?

FX2LP code body:

CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz
FIFOPINPOLAR |= 0x04; //slwr=1,others = 0

PINFLAGSCD = 0xC0; // FLAGD - EP2FF
SYNCDELAY;
PORTACFG |= 0x80;
SYNCDELAY;
IFCONFIG = 0xE3; // usb
SYNCDELAY;
// IFCLKsrc=1 , FIFOs executes on internal clk source
// xMHz=1 , 48MHz operation
// IFCLKOE=1 ,Drive IFCLK pin signal at 48MHz
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// ASYNC=0 , master samples synchronous
// GSTATE=0 , Don't drive GPIF states out on PORTE[2:0], debug WF
// IFCFG[1:0]=11, FX2 in slave FIFO mode

// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG

// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// EP4 and EP8 are not used in this implementation...
EP2CFG = 0xDB; // in iso 1024B 3xbuf
SYNCDELAY;
//EP6CFG = 0x92; // out iso 512B 2xbuf
EP6CFG &= 0x7F;
SYNCDELAY;
EP4CFG &= 0x7F; //clear valid bit
SYNCDELAY;
EP8CFG &= 0x7F; //clear valid bit
SYNCDELAY;

SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;

EP2FIFOCFG = 0x0D; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1
SYNCDELAY;
EP2ISOINPKTS = 0x83; //AADJ = 1, INPPF[1:0] = 3(1,2,3)
SYNCDELAY;
//JTAG Enable and SYNC signals for ZTEX Spartan 6 module 1.1 (FGPA+FX2LP setup)
OEA|=0x02; //Declare PA.1 as output
SYNCDELAY;
IOA|=0x02; //output 1 on PA.1
SYNCDELAY;
OEC|=0x01; //PC.0 as output (SYNC signal)
SYNCDELAY;
IOC|=0x00; //output 0 on PC.0...SYNC signal is LOW
SYNCDELAY;
OEC&=0xFD; //PC.1 as input (Clock changing signal)
SYNCDELAY;

Why is the official instance CYStream.hex unrecognized, no response, or even illegal access error after downloading