Hello 

my Device (Audio-Midi) is not working see other post...so in windows I get unrecognized device and under OSX the 

Chip is not even listed under the USB .

if I boot Linux I get the AN2131SC Anchor Device with  VID/PID correct, but the internal firmware is not loaded into the chip itself.

i have read that the internal RAM and Bootloader of the AN21...can be corrupted and then it stops working.

How can I force a complete reset or erasing of the AN2131SC itself ?

Kindle Maurizio 

Hello ,

I want to make use of the interrupt ISR_Ures(void) interrupt 0.
In the TRM it is mentioned that USB host signals a bus reset 
How is that done ?

Hi

我在固件中设置ep8为输出端点，大小为512字节，零缓冲。但是在实际操作过程中上位机需要发送1024字节才能将端点8写满，读取也是要1024字节才能读空，想请问下这是什么原因？

工作在slave fifo模式，下面是固件代码片段

void TD_Init( void )
{ // Called once at startup

//设置8051的工作频率为48MHz
CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
//配置FIFO标志输出，FLAG G配置为EP2 OUT FIFO空标志
//RTACFG |= 0x80;
//NCDELAY;
//Slave使用内部48MHz的时钟
IFCONFIG = 0x43; //external clk, Slave FIFO interface
SYNCDELAY;

//将EP2断端点配置为BULK-in端点，使用3倍缓冲，1024字节FIFO
//将EP8配置为BULK-OUT端点
EP2CFG = 0xE0; //IN 512 bytes,4* , bulk
SYNCDELAY;
EP4CFG = 0x02; //clear valid bit
SYNCDELAY;
EP6CFG = 0x02; //clear valid bit
SYNCDELAY;
EP8CFG = 0xA1; //Out 512 bytes , bulk
SYNCDELAY;
//复位FIFO
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY;
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY;
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY;
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY;
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
//配置FIFO标志输出，FLAG B配置为EP2 IN FIFO FULL FLAG
PINFLAGSAB = 0xC8; // FLAGB - EP2FF,FLAGA - EP2EF
SYNCDELAY;
//配置FIFO标志输出，FLAG C配置为EP8 OUT FIFO EMPTY FLAG
PINFLAGSCD = 0xFB; // FLAGC - EP8EF,FALGD - EP8FF
SYNCDELAY;
//
PORTACFG |=0x80;
SYNCDELAY;

//所有引脚低有效
FIFOPINPOLAR= 0x00;
SYNCDELAY;
// handle the case where we were already in AUTO mode...
// ...for example: back to back firmware downloads...
// core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's
EP8FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=1
SYNCDELAY; //
EP8FIFOCFG = 0x11; // AUTOOUT=1, WORDWIDE=1
SYNCDELAY; //
EP2FIFOCFG = 0x0D; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1
SYNCDELAY;

EP2AUTOINLENH = 0x02;
SYNCDELAY;
EP2AUTOINLENL = 0x00;
SYNCDELAY;
}

描述符代码片段

HighSpeedConfigDscr:
db DSCR_CONFIG_LEN ;; Descriptor length
db DSCR_CONFIG ;; Descriptor type
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) mod 256 ;; Total Length (LSB)
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) / 256 ;; Total Length (MSB)
db 1 ;; Number of interfaces
db 1 ;; Configuration number
db 0 ;; Configuration string
db 10100000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
db 50 ;; Power requirement (div 2 ma)

;; Alt Interface 0 Descriptor - Bulk IN-OUT
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 0 ;; Alternate setting
db 2 ;; Number of end points
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index This would be nice to add!

;; Bulk IN Endpoint Descriptor
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint 2 and direction IN
db ET_BULK ;; Endpoint type
db 00H ;; Maximun packet size (LSB) 512 byte packets/uFrame
db 02H ;; Max packect size (MSB)
db 00H ;; Polling interval

;; Bulk OUT Endpoint Descriptor
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 08H ;; Endpoint 8 and direction OUT
db ET_BULK ;; Endpoint type
db 00H ;; Maximun packet size (LSB)
db 02H ;; Max packect size (MSB) 512 byte packets/uFrame
db 00H ;; Polling interval

HighSpeedConfigDscrEnd:

图中flagc代表端点8空信号，flagd代表端点8满信号

谢谢

你好

能否提供CY7C68013控制器驱动的步进电机的参考代码？ 驱动芯片采用DRV8436

Is there a program that can configure the CY7C65215-32LTXI USB-Serial Dual CH Bridge by using text commands only on Windows without GUI?

Hello,

I found this forum that mentions the sampling rate of simple and complex GPIOs. To my knowledge, these pin configurations are only available in the main library.

https://community.infineon.com/t5/USB-superspeed-peripherals/FX3-GPIO-Clocks/td-p/191417#:~:text=Simple%20GPIOs%20use%20the%20FX3,a%20maximum%20of%20201.6%20MHz

Does anyone know what the sampling rate of the boot library GPIO pins are? I am trying to sample a 50MHz clock would this be doable?

Thanks,

Hersh

Hello,

I have a 50MHz external clock that is being driven into a GPIO pin on the CYUSB2014-BZXC and was wondering if there was a way to sync this to an output GPIO pin with the BOOT library?

This also raises the question, should I stick with boot or switch to the U3 Library (U3 vs FX3)? I don't necessarily need multithreads or RTOS, but it looks like there is less functionality with boot.

Thanks,

Hersh

Hello,

I have a 50MHz external clock that is being driven into a GPIO pin on the CYUSB2014-BZXC and was wondering if there was a way to sync this to an output GPIO pin with the BOOT library?

This also raises the question, should I stick with boot or switch to the U3 Library (U3 vs FX3)?

Thanks,

Hersh