USB low-full-high speed peripherals Forum Discussions
I am using Windows 7 x64 operating system and cy7c80 controller device with FPGA.I have been able to successfully implement UVC-compliant driver and the next task is building custom class for the video signal.
The host application is compiled by VS2010 SP1.
Also,I have succeeded to implement sort of small test application using CYAPI Streamer example (I am using the latest Cypress USB suite, 3.4.7),in which I have been able to achieve optimal speed and perform desired operations with received data.The problems occur,when I am going to the next stage and that is design the GUI according to my needs and here I face enormous obstacles:
1)Once I try to change Streamer application window form design (even the smallest change) ,several files are stripped off their "Read only" status (I think the most important is Resource.resX) and then ,the hell breaks loose - I got around 90 (!) compilation errors.Doing some tricks such as changing CLR support and adding #include <wtypes.h> and <gdt.h>,that were mentioned in obsolete cypress application note on CyAPI does not help, and I must fallback to previously saved (and untoched) backup copy.Obviously ,using Streamer example as starting point and then tweaking it to my application needs is not a possibility (unless you could provide me some workaround).
2)After abandoning the Streamer basic option , I have tried working around the problem ,by creating a fresh CLR (C++ WinForms ) application from scratch and then adding CyAPI headers.
After another torture with compilation errors and playing around with including header files and playing with CLR support I have been able to get compilation-errors free application.But then I have encountered a very critical compilation error,which at this point is a blocking error:
I have tried to create a CCyUSBDevice instance using the following simple line of code :
CCyUSBDevice *USBDevice = new CCyUSBDevice(NULL);
and I get the following linker errors :
Last summer, after hearing for months that Cypress was going to have an Eclipse based development tool for the FX2LP, I downloaded version 0.0.0 of the "Cypress EZ-USB Suite". The software was incredibly buggy, and obviously only paid lip-service to the FX2LP, but I managed to get it working and do some useful development with it.
Checking back now, I find no mention of these tools for the FX2LP, but only the Cypress EZ-USB FX3 software,
Does the new package include support for the FX2LP?
Was there ever an update to the 0.0.0 release of the EZ-USB Suite that did support the FX2LP? Is there a link to it somewhere?Show Less
I'm experiencing some data corruption from the point I send data to the OUT endpoint and by the time it reaches the fdata pins on the slave FIFO. Let me explain my setup.
I started by following the Synchronous Slave FIFO Streaming Example. So I have an Altera MAX V CPLD acting as a Master FIFO and the FX2 configured as a Slave FIFO with two endpoints. Endpoint 0x02 is configured as an OUT BULK end point and 0x86 is configured as an IN INTERRUPT endpoint with polling interval of 1. You can see the descriptor here https://gist.github.com/ismell/9390416#file-dscr-asm-L95.
The FX2 is configured to auto commit both endpoints. I am using an external clock provided by the CPLD as the FIFO clock. The clock is running at 10MHz. You can see the configuration here https://gist.github.com/ismell/9390416#file-fx2-c-L205.
My application is based off the Streaming Example included in the SDK. It queues up a few async transfers on the IN endpoint and waits for the CPLD to send a packet. https://gist.github.com/ismell/9390416#file-form-cs-L1081 shows the BeginXfer call and https://gist.github.com/ismell/9390416#file-form-cs-L1156 shows the EndXfer call. This is all copied from the example and has not been changed.
The changes do start with analyzeFrameData at https://gist.github.com/ismell/9390416#file-form-cs-L1160. If the frame contains one of the specified commands I want to send a packet on the OUT endpoint. I'm using the synchronous API to do this. You can see my XferData call on the OUT endpoint here https://gist.github.com/ismell/9390416#file-form-cs-L1372. This is where the data corruption is happening. It doesn't happen all the time, but randomly. I have used my logic analyzer to sniff the fdata[7:0] pins on the FX2 to see what it is sending to my CPLD and there is usually one byte that is incorrect.
Does anyone see anything wrong with the way I'm using the API? Is using the synchronous XferData API wrong in this case? Should I be creating an async request for my OUT endpoint?
Any suggestions would be greatly appreciated.
p.s) I'm using an Interrupt IN endpoint because I need to keep latency as low as possible. I have under 1ms between the time the CPLD sends the pkt_end signal to the FX2 and when I have to start writing data back to the CPLD.Show Less
The CY7C68013 is a 3.3V device. The "features" page of the manual says that its inputs are "5V tolerant", but the "absolute maximums" chapter is somewhat ambiguous - it says 5.25V for inputs and Vcc+0.5V for outputs in high-Z state. Every bi-directional port pin, when used as an input, is also an output in high-Z state, so I'm not sure... any help would be appreciated.Show Less
in slave fifo on fx2lp, i have received data.
Why missed 1 data after 2048 data?
you can check attached file.Show Less
Hi. I'm using the DE2-115 FPGA. I'm trying to write my own firmware for the CY7C67200. I finished writing for the ISP1362 and then TerAsic changed the darn chip.
I'm having difficulty reading default values. I am trying to read the hardware revision at 0xC004. It should be 0x0101 + the number of revisions. I believe the chip is revision A, so that would be +0, correctl? When I read the value, I get 0xC008.
Does it matter if the address changes with Chip Select? Is there an FPGA example on this anywhere? I'm having difficulty understanding the difference between the address states (address, data, mailbox, status).
Any help would be greatly appreciated. I've been reading the documents from CY3663, but nothing seems to give me confidence that I'm doing it correctly.