USB low-full-high speed peripherals Forum Discussions
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USB low-full-high speed peripherals
I ultize cy7c68013a chip to fullfil a bulk transfer.I have configured EP2 as OUT endpoint,bulk,quad buffer(4*);ep6 as IN endpoint,bulk,quad bu...
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I ultize cy7c68013a chip to fullfil a bulk transfer.I have configured EP2 as OUT endpoint,bulk,quad buffer(4*);ep6 as IN endpoint,bulk,quad buffer(4*),but now I have confronted a data losing problem.I want to know what registers are related to the transfer speed(or packetsize).
Otherwise,I have read some references and was confused by following packet-related concepts:maxPacketSize,EPxBCL/H,AUTO2/4/6/8INLENGTHL/H.
Thank you for your reply! Show Less
Otherwise,I have read some references and was confused by following packet-related concepts:maxPacketSize,EPxBCL/H,AUTO2/4/6/8INLENGTHL/H.
Thank you for your reply! Show Less
USB low-full-high speed peripherals
Hi, I'm writing an application based on the Screamer example code and I'm seeing strange behavior from the WaitForXfer method. At least...
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Hi,
I'm writing an application based on the Screamer example code and I'm seeing strange behavior from the WaitForXfer method. At least, I think it's strange based on how I've seen WaitForXfer used in the code examples. Also, the documentation doesn't give much in the way of details.
In my program, I'm trying to read a continuous stream of data from a bulk endpoint using the queued overlapped-transfer methodology provided in the Screamer example code (see the code's XferThread, LockNLoad and XferData methods). In fact, I haven't changed much in that section of the code, except for adding a wait loop at the WaitForXfer call and writing the incoming data to file every one cycle through the queue.
My problem is that WaitForXfer always returns FALSE, meaning it has timed-out waiting for the OS to signal that the requested data has arrived. This is wrong, because I can see in USBlyzer (a sniffer program) that the requests are going out on the USB (from the preceding BeginDataXfer calls) and that the expected data is arriving from the device. My program sits in a loop, calling WaitForXfer multiple times and waiting for it to return TRUE, so that the program might proceed to call FinishDataXfer and write the data to a file. Even though the data has already come in, WaitForXfer never indicates its presence (seems to me that it should), and so my program stays in the wait loop. I'm giving WaitForXfer a reasonable timeout of 500ms. Since CyUSB is a black-box, I'm not sure how to troubleshoot this any further.
Is my understanding of WaitForXfer's intended behavior correct?
Can anyone provide some insight into what the problem might be?
I'm using Windows XP and SuiteUSB 2.0.
Thanks
Show Less
I'm writing an application based on the Screamer example code and I'm seeing strange behavior from the WaitForXfer method. At least, I think it's strange based on how I've seen WaitForXfer used in the code examples. Also, the documentation doesn't give much in the way of details.
In my program, I'm trying to read a continuous stream of data from a bulk endpoint using the queued overlapped-transfer methodology provided in the Screamer example code (see the code's XferThread, LockNLoad and XferData methods). In fact, I haven't changed much in that section of the code, except for adding a wait loop at the WaitForXfer call and writing the incoming data to file every one cycle through the queue.
My problem is that WaitForXfer always returns FALSE, meaning it has timed-out waiting for the OS to signal that the requested data has arrived. This is wrong, because I can see in USBlyzer (a sniffer program) that the requests are going out on the USB (from the preceding BeginDataXfer calls) and that the expected data is arriving from the device. My program sits in a loop, calling WaitForXfer multiple times and waiting for it to return TRUE, so that the program might proceed to call FinishDataXfer and write the data to a file. Even though the data has already come in, WaitForXfer never indicates its presence (seems to me that it should), and so my program stays in the wait loop. I'm giving WaitForXfer a reasonable timeout of 500ms. Since CyUSB is a black-box, I'm not sure how to troubleshoot this any further.
Is my understanding of WaitForXfer's intended behavior correct?
Can anyone provide some insight into what the problem might be?
I'm using Windows XP and SuiteUSB 2.0.
Thanks
Show Less
USB low-full-high speed peripherals
I'm using the CY7C64713, I only need Endpoint0 and Endpoint1.. I would like to use the 4KBytes of RAM, available for unused endpoints 2,4,6...
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I'm using the CY7C64713, I only need Endpoint0 and Endpoint1..
I would like to use the 4KBytes of RAM, available for unused endpoints 2,4,6,8 as regular data RAM. Is this possible?
It seems like I can use following chunks without problem :
0xF000-0xF3FF
0xF400-0xF5FF
0xF800-0XFBFF
0xFC00-0xFBFF
I can't read/write correctly in the chunks
0xF600-0xF7FF
0xFC00-0xFFFF
Why is this? How should I configure the unused endpoints (EP2CFG ... EP8CFG) in order to enable use of the complete block of RAM?
Thanks! Show Less
I would like to use the 4KBytes of RAM, available for unused endpoints 2,4,6,8 as regular data RAM. Is this possible?
It seems like I can use following chunks without problem :
0xF000-0xF3FF
0xF400-0xF5FF
0xF800-0XFBFF
0xFC00-0xFBFF
I can't read/write correctly in the chunks
0xF600-0xF7FF
0xFC00-0xFFFF
Why is this? How should I configure the unused endpoints (EP2CFG ... EP8CFG) in order to enable use of the complete block of RAM?
Thanks! Show Less
USB low-full-high speed peripherals
we are having trouble making the sx2 talk to the computer using a different configuration. If anyonewas able to do this would you care to info...
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we are having trouble making the sx2 talk to the computer using a different configuration. If anyonewas able to do this would you care to inform me what you did?
Thank you,
jem Show Less
Thank you,
jem Show Less
USB low-full-high speed peripherals
I'm using the example application USB Control Center with the reference board using the FX1 part... The CyConsole can see the part, download e...
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I'm using the example application USB Control Center with the reference board using the FX1 part... The CyConsole can see the part, download etc. Works great... But When using the USB Control Center is does not see the part. The Generic USB device is not a HID correct? Hence it does not display using the device? I have all of the options selected.. I even copied the code... and it still does not work...
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USB low-full-high speed peripherals
I'm looking for the EzUSB.sys driver development tools. Specificaly I want to be able to build the EzUSB.sys driver if possible. If not possib...
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I'm looking for the EzUSB.sys driver development tools. Specificaly I want to be able to build the EzUSB.sys driver if possible. If not possible then I would settle for the EzUSB.sys driver documentation and include files.
Thanks,
-Reed Show Less
Thanks,
-Reed Show Less
USB low-full-high speed peripherals
We are trying to reconfigure the endpoints (only use EP2, EP4, EP6) instead of using the default configuration. We have already wrote to their...
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We are trying to reconfigure the endpoints (only use EP2, EP4, EP6) instead of using the default configuration. We have already wrote to their respective registers to change that. However, file transfers don't seem to work. My question is, to reconfigure the endpoints what steps should be done besides writing to their registers. Do we need to address pktlen(reg 0x0A-0x11) and flush(reg 0x20)? I mean, what else should be considered in order to reconfigure the endpoints.
Thank you.
Jem Show Less
Thank you.
Jem Show Less
USB low-full-high speed peripherals
hi, I am new to design side. so can u please help me out? I am using CY7C68013A. i want to interface controller with fpga using slave...
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hi,
I am new to design side. so can u please help me out?
I am using CY7C68013A.
i want to interface controller with fpga using slave fifo interface. but i do not know how to configure the controller and what data content should i write into controller registers to set it as a slave fifo? How can i configure the controller? Do i have to use any EEPROM to configure the controller? If so, then what registers value i have to load in EEPROM? And how EEPROM will configure the controller?
Thanks & Regards Show Less
I am new to design side. so can u please help me out?
I am using CY7C68013A.
i want to interface controller with fpga using slave fifo interface. but i do not know how to configure the controller and what data content should i write into controller registers to set it as a slave fifo? How can i configure the controller? Do i have to use any EEPROM to configure the controller? If so, then what registers value i have to load in EEPROM? And how EEPROM will configure the controller?
Thanks & Regards Show Less
USB low-full-high speed peripherals
hi guys, recently, I'm developing a usb project, in which Cy7c68013A-128AXC is used to communicate with FPGA through slave fifo interfa...
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hi guys,
recently, I'm developing a usb project, in which Cy7c68013A-128AXC is used to communicate with FPGA through slave fifo interface,
in the 68013, EP2 is configured as 512 bytes double buffered mannual out fifo, EP6 is configured as 512 byte double buffered auto-in fifo, IFCLK is coming from external.
after painful debugging, I saw very strange behavior in the slave fifo interface:
when FPGA read data from 68013 through slave fifo interface, we must set the SLOE bit of FIFOPINPOLAR register to be '1', after that, FPGA can correctly read data from slave fifo interface no matter what value appears in SLOE pin, even though drive '0' on SLOE pin.
otherwise, if we set the SLOE bit of FIFOPINPOLAR register to be '0', then we can never read data out from slave fifo even we drive SLOE pin to '0', the data bus on slave fifo looks like in HighZ state.
when FPGA write data into 68013, the condition is contrary to read data from 68013. we must set the SLOE bit of FIFOPINPOLAR register to be '0', after that, FPGA can correctly write data into 68013 through slave fifo interface no matter what value appears in SLOE pin, even though drive '0' on SLOE pin.
otherwise, if we set the SLOE bit of FIFOPINPOLAR register to be '1', then we can never write data into 68013 through slave fifo interface, even we drive SLOE pin to '0'.
and I'm sure that the SLOE pin connection is ok, it's not floating.
following is TD_init() in 68013 firmware, is there any wrong configuration??
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1
SYNCDELAY; //
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; //
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY;
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; // //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;
// set the slave FIFO interface to 48MHz, use external clock
IFCONFIG = 0x43;
SYNCDELAY;
EP2FIFOCFG = 0x01; // mannual out
SYNCDELAY;
EP2CFG = 0xA2;
SYNCDELAY;
EP6FIFOCFG = 0x09; // autoin
SYNCDELAY;
EP6CFG = 0xE2;
SYNCDELAY;
// !!!!!! when external fifo master read data from slave interface, the SLOE bit in register FIFOPINPOLAR must set to be 1, FIFOPINPOLAR = 0x10
// !!!!!! when external fifo master write data into slave interface, the SLOE bit in register FIFOPINPOLAR must set to be 0, FIFOPINPOLAR = 0x00
FIFOPINPOLAR = 0x00;
SYNCDELAY;
EP6AUTOINLENH = 0x02; // you can define these as you wish,
SYNCDELAY; // to have the FX2 automatically limit IN's
EP6AUTOINLENL = 0x00;
SYNCDELAY;
SYNCDELAY;
EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY;
EP2BCL = 0x80;
SYNCDELAY;
// enable dual autopointer feature
AUTOPTRSETUP |= 0x01;
Rwuen = TRUE; // Enable remote-wakeup
}
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recently, I'm developing a usb project, in which Cy7c68013A-128AXC is used to communicate with FPGA through slave fifo interface,
in the 68013, EP2 is configured as 512 bytes double buffered mannual out fifo, EP6 is configured as 512 byte double buffered auto-in fifo, IFCLK is coming from external.
after painful debugging, I saw very strange behavior in the slave fifo interface:
when FPGA read data from 68013 through slave fifo interface, we must set the SLOE bit of FIFOPINPOLAR register to be '1', after that, FPGA can correctly read data from slave fifo interface no matter what value appears in SLOE pin, even though drive '0' on SLOE pin.
otherwise, if we set the SLOE bit of FIFOPINPOLAR register to be '0', then we can never read data out from slave fifo even we drive SLOE pin to '0', the data bus on slave fifo looks like in HighZ state.
when FPGA write data into 68013, the condition is contrary to read data from 68013. we must set the SLOE bit of FIFOPINPOLAR register to be '0', after that, FPGA can correctly write data into 68013 through slave fifo interface no matter what value appears in SLOE pin, even though drive '0' on SLOE pin.
otherwise, if we set the SLOE bit of FIFOPINPOLAR register to be '1', then we can never write data into 68013 through slave fifo interface, even we drive SLOE pin to '0'.
and I'm sure that the SLOE pin connection is ok, it's not floating.
following is TD_init() in 68013 firmware, is there any wrong configuration??
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1
SYNCDELAY; //
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; //
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY;
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; // //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;
// set the slave FIFO interface to 48MHz, use external clock
IFCONFIG = 0x43;
SYNCDELAY;
EP2FIFOCFG = 0x01; // mannual out
SYNCDELAY;
EP2CFG = 0xA2;
SYNCDELAY;
EP6FIFOCFG = 0x09; // autoin
SYNCDELAY;
EP6CFG = 0xE2;
SYNCDELAY;
// !!!!!! when external fifo master read data from slave interface, the SLOE bit in register FIFOPINPOLAR must set to be 1, FIFOPINPOLAR = 0x10
// !!!!!! when external fifo master write data into slave interface, the SLOE bit in register FIFOPINPOLAR must set to be 0, FIFOPINPOLAR = 0x00
FIFOPINPOLAR = 0x00;
SYNCDELAY;
EP6AUTOINLENH = 0x02; // you can define these as you wish,
SYNCDELAY; // to have the FX2 automatically limit IN's
EP6AUTOINLENL = 0x00;
SYNCDELAY;
SYNCDELAY;
EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY;
EP2BCL = 0x80;
SYNCDELAY;
// enable dual autopointer feature
AUTOPTRSETUP |= 0x01;
Rwuen = TRUE; // Enable remote-wakeup
}
Show Less