USB low-full-high speed peripherals Forum Discussions
Get PipeInfo
Pipe: 0 Type: ISO Endpoint: 2 OUT MaxPktSize: 0x400
Pipe: 1 Type: ISO Endpoint: 6 IN MaxPktSize: 0x400
I am transferring the data through ISO TRANS pipe 0 with 1024 length, Packet size 1024 with 1 packet with the same hardware used for Bulk mode.
Isoc OUT Transfer
Isoc OUT failed
Would anybody tell me why the transfer get failed? Show Less
Why HCNTL[1:0] connect PA[3:2] in this case? It doesn't make sense,cause HCNTL[1:0] is the address bus of the HPI,but the address[1:0] of CY7C68013A is PA[5:4]. So could any body explain this?Thank you!
Show LessI have a 24 MHz crystal oscillator attached to the XTAL_IN and XTAL_OUT of the CY68013 128 pin package. The voltage level on the XTAIN_IN side is around 3.3 Volts peak-to-peak. On the XTAL_OUT side I am only seeing 2V. My CLKOUT pin then puts out around 140 MHz, which is WAY above the default of 12 MHz. I see CLKOUT intially start at 12 MHz(default) then change to 140 MHz. Why is this clock so fast? Could the 2 Volts peak-to-peak be the issue? Why am I only seeing 2V peak-to-peak?
Thank You.
Show LessI would like to use the above driver for a USB device containing a Cypress uproc (EZ-USB FX2), attached to a Windows 7 64-bit host. I think this is a Kernel-mode driver, but I am not positive. Can someone confirm that it is? Also, to deploy the driver to customers running our hardware from the same type of host, I think that the driver must be "signed." Being that the driver is "WHQL certified" is there another requirement to use this commercially, such as "kernel mode code signing?"
Show LessHi all,
I'm trying to realize this design found on TRM, to source a packet from firmware with autoin and isochronous transfer (in order to create an header). Unfortunately only a small part of the firmware-created packets are sent.
Have you got some clue to get this design working?
while( !( EP68FIFOFLGS & 0x20 ) ) { // EP8EF=0, when buffer not empty ; // wait ‘til host takes entire FIFO data } FIFORESET = 0x80; // initiate the “source packet” sequence SYNCDELAY; FIFORESET = 0x06; SYNCDELAY; FIFORESET = 0x00; EP8FIFOBUF[ 0 ] = 0x02; // <STX>, packet start of text msg EP8FIFOBUF[ 1 ] = 0x06; // <ACK> EP8FIFOBUF[ 2 ] = 0x07; // <HEARTBEAT> EP8FIFOBUF[ 3 ] = 0x03; // <ETX>, packet end of text msg SYNCDELAY; EP8BCH = 0x00; SYNCDELAY; EP8BCL = 0x04; // pass newly-sourced buffer on to host Thanks in advance.Show Less
Hi all, thanks in advance for the help. I am trying to configure the CY7C67300 (EZ-USB) on a Xilinx XUPV5 FPGA board. I am just trying to run the de2 design example to setup the FPGA as a peripheral. When I try to program the EEPROM with the bin file using qtui2c I get the error "USB Device not found". I assume this is because I am not using the correct driver? Currently the part is loading cyusb.sys that I got from http://www.cypress.com/?rID=34870. The documentation says I have to use cyusbgen.sys, however I am on Windows 7 x64 so I can't get this driver to load. Is there another driver that I can try, or a way to get this to work with cyusb.sys? Thanks.
Show LessHi everyone.
I'm using old ezusb.sys driver to communicate with CY7C68013 USB chip.
Where can i find a documentation on a ezusb.sys?
I faced with some problems using it. I'm doing send and receive operations (BULK transfer). The question is what happens with packets if they are send to PC but not read with IOCTL_EZUSB_BULK_READ. Does ezusb.sys uses an internal buffer?
Where can i read about theese things?
Thanks in advance.
Show LessHello,
Is there a document somewhere on how to configure the device descriptors in dscr.a51? Which bits represent which options?
Would there be a way to define the device descriptors not in dscr.a51, but in C-software. I would like to synchronize the device descriptors to the actual settings, which are done in C-code.
All of these are done at the very start of the C-software and are not changed afterwards, so theoretically there is no reason that this would not be possible.
Show Less