USB low-full-high speed peripherals Forum Discussions
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i'm using the slave FIFO interface for bulk auto-in transfers directly from an FPGA to the host, in asynchronous mode.
Right after the FULL flag asserts, the FULL flag deasserts and the EMPTY flag asserts simultaneously.
I have attached a screen shot of the waveforms.
Any ideas of what could cause this?
Show LessHi,
In my project based on cy7c68013a I need from time to time to switch endpoint EP2 direction from OUT
to IN and vise versa.
I do it through the following steps:
void TD_Init(void) // Called once at startup
{
CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, disable CLKOUT
SYNCDELAY; // see TRM section 15.14
IFCONFIG=0xcb;
SYNCDELAY; // see TRM section 15.14
REVCTL=0x03;
SYNCDELAY; // see TRM section 15.14
//EndPoints
FIFORESET=0x80;
SYNCDELAY;
FIFORESET=0x82;
SYNCDELAY;
FIFORESET=0x84;
SYNCDELAY;
FIFORESET=0x00;
SYNCDELAY;
EP1OUTCFG = 0xA0;
SYNCDELAY; // see TRM section 15.14
EP1INCFG = 0xA0;
SYNCDELAY; // see TRM section 15.14
EP2CFG=0xa2; //valid, out, bulk, 512, 2 x buff
SYNCDELAY;
EP4CFG=0xa0; //valid, out, bulk, 512, 2 x buff
SYNCDELAY;
EP6CFG=0x00; //invalid
SYNCDELAY;
EP8CFG=0x00; //invalid
SYNCDELAY;
OUTPKTEND=0x82;
SYNCDELAY;
OUTPKTEND=0x82;
SYNCDELAY;
OUTPKTEND=0x84;
SYNCDELAY;
OUTPKTEND=0x84;
SYNCDELAY;
EP2FIFOCFG=0x18; //AUTOIN,AUTOOUT,8-bit data bus
SYNCDELAY;
EP4FIFOCFG=0x00; //manual, 8-bit data bus
SYNCDELAY;
//to define buswidth==8-bit for all EP (disabled too !!)
EP6FIFOCFG=0; //8-bit data bus
SYNCDELAY;
EP8FIFOCFG=0; //8-bit data bus
SYNCDELAY;
EP2BCL = 0x80; // arm EP2OUT
SYNCDELAY;
EP2BCL = 0x80;
SYNCDELAY;
EP4BCL = 0x80; // arm EP4OUT
SYNCDELAY;
EP4BCL = 0x80;
SYNCDELAY;
//Flags
PINFLAGSAB=0xc8; //FlagB - Full for EP2; FlagA - Empty for EP2
SYNCDELAY;
PINFLAGSCD=0x04; //FlagD - PA7 ; FlagC - Prg. for EP2
SYNCDELAY;
FIFOPINPOLAR=0x00;
SYNCDELAY;
//Port D
OED=0xff; //OutputEnable port D (1-output, 0-input)
IOD=0x00;
}
void TD_Poll(void) // Called repeatedly while the device is idle
{
unsigned char tmp;
if(!(EP2468STAT & 0x04))
{
tmp=EP4FIFOBUF[0];
SYNCDELAY;
OUTPKTEND=0x84;
SYNCDELAY;
OUTPKTEND=0x84;
SYNCDELAY;
IOD=tmp;
if(tmp==0x01) //switch EP2 to IN
{
SYNCDELAY;
FIFORESET=0x80;
SYNCDELAY;
SYNCDELAY;
EP2CFG=0xe2; //valid, in, bulk, 512, 2 x buff
SYNCDELAY;
FIFORESET=0x80;
SYNCDELAY;
FIFORESET=0x82;
SYNCDELAY;
FIFORESET=0x00;
SYNCDELAY;
INPKTEND=0x82;
SYNCDELAY;
INPKTEND=0x82;
SYNCDELAY;
EP2FIFOCFG=0x18; //AUTOIN,AUTOOUT,8-bit data bus
SYNCDELAY;
EP2AUTOINLENH=0x02;
SYNCDELAY;
EP2AUTOINLENL=0x00;
EP2BCH=0x00;
SYNCDELAY;
EP2BCH=0x00;
SYNCDELAY;
EP2BCL=0;
SYNCDELAY;
EP2BCL=0;
SYNCDELAY;
}
else //switch EP2 to OUT
{
SYNCDELAY;
EP2CFG=0xa2; //valid, out, bulk, 512, 2 x buff
SYNCDELAY;
SYNCDELAY;
}
}
}
Thus, I use EP4 (BULK, OUT, 512x2, MANUAL MODE, 8-bit) for switching EP2 (BULK, OUT, 512x2, AUTO MODE, 8-bit) direction and at the same time for changing status of pin D0 for its use by external device.
My question: why after switching from OUT to IN the FULL FLAG always becomes active (low)?
Thank you for your help
Victor
Will an encore II part show up on the USB as unprogrammed... like an FX2 part does?
Hi,
I am trying to speed up my FX2 firmware and trying to clean up the code. I found that SYNCDELAY macro is used very often in my code and also in firmware examples given by Cypress. For example, code below is taken from C:\Cypress\Cypress Suite USB 3.4.7\Firmware\Bulkloop\bulkloop.c
... EP2CFG = 0xA2; SYNCDELAY; EP4CFG = 0xA0; SYNCDELAY; EP6CFG = 0xE2; ...
As far as I understand from TRM sections 15.15, such a delay should be used in situation when you write some register A then read/write other register B and register B depends in some way on register A. This delay just gives a time for internal hardware to "catch" new value & update all others that depend on it.
So in the given example because we only write registers, there is no need for such delays, right? Please correct me if I am wrong.
Best regards, Arturas
Show LessI want to know what exactly is the format of IIC files. Like is it in a HEX format or binary format. And I would also like to know how exactly the conversion happens from HEX file to IIC file. I need to add a routine to calculate checksum for an IIC file, is it possible ?
i get to know
00000000 c2 47 05 31 21 00 00 04 00 04 00 00 02 32 81 32
- c2: boot byte, poke eeprom content to ram
- 3 x 2 bytes of vid, pid, did (here: set by firmware)
- 04: config byte, connected, 48 mhz, not inverted, 100 khz i2c
- 00 04 00 ...: should be first firmware bytes
00003450 d6 00 02 10 d6 00 02 10 d6 00 80 01 e6 00 00
- e6 00 00: reset command, 0xe600 is the cpucs addr
Please help me out with this !!!!!!!!!!!!
Best Regards,
Show LessI am using the Slave FIFO to do bulk transfers from the host to an FPGA. When I send a packet from the host I am able to read the expected number of bytes from the Slave FIFO. However instead of the expected data I get an alternating sequence of bytes. Further, there are 2 sequences, which alternate with each packet sent.
For example:
And so on.
The endpoint is double buffered, so maybe it switches between sequences when the buffer changes?
I verified with a USB analyzer that the packet sent to the FX2LP is correct.
Any ideas why I get these symptoms?
Show LessHello,
I have a problem with USB video camera, that uses chip CY7C68013A-56PVXC :
> Camera not responding, when are connected to the PC.
> I replaced a XTAL - no change.
> I don't see broken components or tracks on PCB.
> Voltages of 1V8 & 2V8 test points are OK.
> Manifacturer of camera offer me replacement PCB, but I want to try repair first.
I have a second, working camera with exactly the same hardware.
> Is it possible to buy new chip CY7C68013A-56PVXC,
solder on PCB and copy firmware code from working camera?
> Is it exist copy protection in CY7C68013A-56PVXC,
that will prevent duplicating of firmware from one chip to another ?
Thanks in advance!
Valentin
hello,when i download cystream.hex locate in C:\Cypress\Cypress Suite USB 3.4.7\Firmware\CyStreamer,it remind to install .inf file,i have try all of the inf file in Cypress directory,but it donot work.
Show LessHi,
I've problem with using PF Flag with GPIF FlowState.
System overview:
- GPIF works as master
- endpoint EP6 IN, bulk, 2x1024B
- externally GPIF is connected to FPGA (8-bit, 48MHz from Cypress)
Settings in C51 code:
- configure GPIF to use PF flag from EP6 fifo: EP6GPIFFLGSEL = 0x00;
- setting treshold for PF Flag:
EP6FIFOPFH = 0xC1; // 0b11000011
SYNCDELAY;
// EP6 FIFO Programmable Level Flag - low byte of Treshold byte count
EP6FIFOPFL = 0xFF; // Treshold 0x1FE = 510 bytes
SYNCDELAY;
- triggering GPIF transfer for 1024B
GPIFTCB1 = 0x04; SYNCDELAY;
GPIFTCB0 = 0x00; SYNCDELAY;
Setup_FLOWSTATE(GPIF_FIFO_RD); SYNCDELAY;
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
{;}
GPIF FIFO Read waveform (see screenshots):
- DecisionPoint use TCXpire (RDY.5 is enabled for that)
- I use FlowState in state2 to continously read data
- FlowState checks EMPTY0 Flag (line from FPGA is constant '0') and FIFOFlag (should be PF in my example)
Problem is, that GPIF transfer seen an Logic Analyzer doesn't response on FIFOFlag as I expected.
It's no matter what is the treshold for Programmable Flag (I try 1023, 1000, 512, 510).
FlowState should change states of CTL lines (RD and CS) to 'high' after specified by treshold no of byte transfered to EP6 FIFO, but I see that CS and RD lines are 'low' until TCXpire finishes GPIF transfer (1024 bytes in my example)
Questions:
Why FlowState doesn't response on FIFOFlag ( Programmable Flag ) in FlowState?
Is this related to "passing through IDLE state"?
Have anybody used Programmable Flag in GPIF?
I'll be gratefull for help
Best regards
Karol
Show Less