USB low-full-high speed peripherals Forum Discussions

Hi all, I'm new to USB development and really hope I can find some help here.

I'm working on developing a board which has already been fabricated and populated with the CY7C68013A-128AXC.

I need to read out data from from FPGA RAM to a host application. (I've been using VC ++ 2010 to try to do this)

Ports PB and PD are my 16 bit data lines from the FPGA to fx2.  Ideally I want flaga and flagb to go high to inisiate read and write oporations in the FPGA, but most important for me is passing the data from port PB and PD, and initiating a 48Mhz clk from IFCLK. I've tried AN61345 however the FIFOADR pins are not connected to anything on my board, so I assume the example will not work.

Is is possible to write my software to configure the cy76c8 registers to properly handle the data transition and IFCLK when run? 

Thus far, using CYAPI.lib I have not been able to recieve data from the FPGA. Any help is appreciated.

Thanks

Sam

Hi, 

I am working on Cypress Cy7C68013A high speed controller. How can I configure the configure the size of the endpoint buffer to be 64bytes (as in full speed), for the bulk transfer. My host also supports USB 2.0 high speed, but due to the typical nature of the project, I need to limit the endpoint size to 64bytes. How can I do this ? 

Thank You

Our project uses a NX2LP-Flex device and a Nand Flash device. On our prototype board, the Nand Flash device is the 4K bytes/Page device. When we are ready to go to production, the 4K bytes/page Nand Flash devices become obsolete. The Nand Flash device vendor forcing us (leave us no choice) to use the 8K bytes/Page MLC NAND Flash devices. The NX2LP-Flex firmware we got from Cypress can support up to 4K bytes/page only. Any help will be appreciated to enhance the NX2LP-Flex Firmware and the programming tool to support the new, 8K bytes/Page, Nand Flash devices.

I have purchased three FX2LP development boards for hobby use from e-bay. These are sold as:

EZ-USB FX2LP CY7C68013A USB Development Core Board Logic Analyzer EEPROM

Any documentation I find says these chips have 16kB RAM, but I can only access bottom 8kB, the range 0x0000 to 0x1fff. Any writes to RAM region 0x2000 to 0x3fff are ignored. Reads seem to return back the same 16bit value for any address. This happens with both 0xA0 vendorcode over USB and executing 8051 program code.

If my build toolchain places descriptors at over 0x2000, the device will disconnect and renumerate, but fails to setup USB with new descriptors. Same code with descriptors moved below 0x2000 works as expected.

LCSOFT CY7C68013A MINI BOARD

CY7C68013A-56PVXC
B 04 PHI 1125
CYP 631702

Can you tell if these markings are valid for Cypress manufactured chips and if there is any related errata with the revision?

Is there some (un)documented bootstrap that could explain this behaviour?
 

Hi All,

If you are using the FX2LP in Linux platform please refer to the following link for downloading the GUI and driver to download the code into FX2LP. Download the FX3 SDK for Linux, it provides the tools for FX2LP too.

http://www.cypress.com/?rID=57990

Regards,

sai krishna.

Hi all

I am designing an application using CY7C68013A that must support high-bandwidth isochronous OUT transfers. Data should be moved out of CY7C68013A to a FPGA. I have implemented device descriptors, the host recognizes the CY7C68013A and loads driver (USB audio), and when I run an application on host (audio player), it seems to send out the data just. The interface between CY7C68013A and FPGA is still TBD, so on this early stage I just want to make sure that the correct data arrives to endpoint. Can someone post a minimalistic example of how I setup the registers, and check the arrived data packets and then discard them?

 Hi,Sir.

I plug in a FX2 board  in PC and install usb driver automatically, it is ok and when I browser Device manager(windows XP )it also show"Cypress EZ-USB FX2(68613)-EEPROM missing".

but Cypress suit USB 3.4.7 issue:USB control center cannot find Cypress EZ-USB FX2(689613)-EEPROM missing, but when I lauch old EZ-USB Control Panel, it is ok?

Anybody can tell why?

Hello

I have connected the USB controller with a Spartan6 FPGA, I have configured this connection for can to initialize the FPGA from PC USB interface with CY7C68013A, I send the bitstream through USB controller. The problem start when the driver hang out it always after in 1Mbyte transfer.

In other case the same interface with old FPGAs with SPARTAN3,SPARTAN2, VIRTEX4, don't need more than 1MByte bitstream and I haven't any problem with them.

I dont know which are the problems?  had you had any same problem? and which are the solutions?

thanks

Best regards

 Hallo Guys,

I ran into some problems last 3 weeks while trying to implement the salve fifo synchronous read module on my fpga using verilog. 

AIM of this project:

Transfer data from PC(matlab file) through c# program(using xferdata()) to the cypress usb. FPGA implements a read module to read data from EP6 and save in a FIFO-memory(IPCORE) for further processing.

Problem:

After setting the SLOE(active low) and SLRD(active low) as required(Cypress manual), the data on the BUS doesn't really change. I used Chipscope from Xilinx for debugging and i got the following simulation(see pdf  file).

As u can see from the simulation, although sloe and slrd shows that different values where supposed to be put on the bus, only 7373 is present at all times. why?

note: the status signal in the simulation is used to make sure that the slrd signal is asserted for exactly one clock circle meaning the cypress usb-device(Fx2) should increase pointer to next value in fifo(EP6) and sloe means it should move into the fd_bus.

-The usb_fd bus usually shows a different value that was never transmitted.(FD99)why?

-after resetting the usb device, the usb_bus shows 7FFF (I used 16 bits bus)why?

-I also noticed that when I changed the REVCTL = 0x03 in the TD_Init(), my endpoint doesn't work. USB Control Center throws an error (BULK OUT transfer ,BULK OUT transfer failed with Error Code:997) but when I comment it out, it works fine. (EP2 is of no use to me at the moment)

Please guys I have been working on this for weeks and I really need urgent help.

Any help will be greatly appreciated

Thanks in advance 

Mathias