USB low-full-high speed peripherals Forum Discussions
Hi,
I am working on Cy7C680-13A usb 2.0 high speed controller. I would like to brief on my system before coming into the problem.
My system has one endpoint (EP2), configured as IN endpoint.
I have used the following lines of codes to enumerate device as a full speed, so that even I plug my USB 2.0 high speed device into a USB high speed host, the device will get enumerated as a full speed, and not high speed, which is a requirement of my project.
USBCS |= 0x08;
EZUSB_Delay(1500);
CT1 |= 0x02;
USBCS &=0xF7;
I am trying to interface an externel master (a cmos camera sensor) to the usb device controller in asynchronous mode. The clock from the externel master is connected to SLWR signal, where I am expecting the external master to write to the IN endpoint FIFO. The SLWR pin is toggled at the rate of 320ns.
Now the problem is,
For the below mentioned code written in TD_Poll( ), I am not able to get the USB device enumerated.
while(!(EP24FIFOFLGS & 0x04)); //check for programmable flag in EP2
{
SYNCDELAY;
EP2BCH = 0x00; //commiting the packet
SYNCDELAY;
EP2BCL = 0x40;
SYNCDELAY;
}
I find that the program is waiting indefinitely at the while loop mentioned in line 1 (things work fine once I comment of the while loop).
Here is how I have configured my programmable flag in TD_Init ( ).
EP2FIFOPFH = (bmBIT7 | bmBIT6); SYNCDELAY;//setting DECIS and PKTSTAT
EP2FIFOPFL = 0x40; SYNCDELAY;
In the above programmable flag configuration, I expect the TD_Poll( ) to come out of while loop once a size of 64 bytes gets filled in EP2. But this is not happening. The program is getting hang inside the while loop mentioned above.
Why is this happening ? Am I missing anything in programmable flag ?
Thank You
Show LessHello
I now design a product use cy7c68013A. when the board is connect to PC, The PC can identify the USB device. And I also can download the Hex file. In my code,I need config two cmos sensor with I2C BUS.So I add the I2C code in TD_INIT function. But I can not find any wave in I2C BUS. So I doubt that the code maybe is not run. So I write a very small progran to test if the chipo is run. the program is :
#include "E:\cypress\usb\target\inc\fx2.h"
#include "E:\cypress\usb\target\inc\fx2regs.h"
//#define ALLOCATE_EXTERN
sbit SDA=IOC^7; /*模拟I2C数据传送位*/
sbit SCL=IOC^6; /*模拟I2C时钟控制位*/
void delay_1ms()
{
unsigned int j ;
for(j=150;j>0;j--);
}
void delay_ms(unsigned int i)
{
for(;i>0;i--)delay_1ms();
}
main()
{
//PORTCCFG=0x00;
OEC=0xFF;
while(1)
{
SDA=1;
SCL=1;
delay_ms(5);
SDA=0;
SCL=0;
delay_ms(5);
}
}
And I also can not measure any wave in I2C BUS.
So please help me ? Where I had made some mistake?
Show LessHi,
Iam working with FX2 . My firmware script download by the driver for Windows Xp works fine. We changed the operating system to Windows 7. It doesn't work anymore .I am using the correct driver for windows 7. When I update the driver with the inf file , it loads both Cyusb.sys and Mydevice.spt but the driver fails to download it automatically and I had to download the firmware manually. I have attached the .inf file . Can you tell the what the problem is and right dir to place the files? I have placed MyDevice.spt in the following folder
\system32\MyDevice\MyDevice.spt"
and CyUsb.inf in the \ D \ Cypress\ CyUsb.inf
Punitha
Show LessIs there a simmilar way to re-enumerate a NX2LP device as a FX2 device?
I am trying to make a INF file which will execute a script at start-up to download the firmware. I am trying it on a 64-bit Windows 7 machine. I obtained the CYUSB.SYS from Cypress Suite USB 3.4.7\Driver\bin\wxp\x64. I used the INF file under Subheading "Execute a script at start-up" in Section "Modifying CyUSB.INF" of "Cypress CyUsb.sys Programmer's Reference" as the template. I have only modified the VID and PID in the INF file. I have also add a string for the second VID_XXXX&PID_XXXX.DeviceDesc (see attached INF file). I also put a script "MyDevice.spt" for firmware download in the same directory of the INF file. The script has been tested successfully using Cyconsole. I am using No EEPROM mode for startup
As the CYUSB.SYS had not been signed, I started the Windows with F8 pressed and then bypassed the Windows driver signature enforcement. Then I plugged the hardware into the USB port, I opened the Windows Device Manager and guided it to the INF file. The driver was installed successfully. But the hardware was only displayed in the first VID&PID in the Windows Device Manager. Therefore, I manually dowloaded the firmware using Cyconsole, then I saw the hardware displayed in the second VID&PID and the firmware worked fine. However, I plugged out hardware and replugged it in, the hardware was displayed in its first VID&PID without the firmware downloaded. I restarted the computer and tried for a few times and still encountered the same problem. It looked like the firmware script was not executed automatically at startup.
What did I do wrong? Any suggestion is highly appreciated!
Device manager show it is ok in Unversal Serial Bus controllers, but USB Control Center cannot find it.I cannot paste the picture. because image button usage is too complex.
Show LessHi,
I am working on Cy7C68013-A usb HS controller. I need to issue a vendor command, where I am expecting an integer count value (int final_count). The value of "final_count" can comfortably go beyond 255. But since EP0BUF[0] supports only a maximum value of 255 (8 bits), I am finding trouble to get any value beyond 255.
Where can I assign my "final_count" variable, so that I can correctly read the integer value even if it crosses the 255 limit.
I have my vendor command function as follows:
switch (SETUPDAT[1])
{
case 0xAA:
EP0BUF[0] = final_count;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
break;
}
In the above case, the EP0BUF[0] has a limit of 255, which will assign incorrect value from my "final_count". The "final_count" value can go near to 2000.
Please give me a solution, where I can read the value of "final_count" on issuing a vendor command ?
Thank You
Show Lesshi,
i am using FX2lP 56-pin package.
I have implemented loopback and streamin examples from the AN61345 . Spartan3E FPGA and fx2lp configuration is done according to the AN61345 .
slave.c is downloaded successfully in the eeprom and detected on Cypress USB Console.
i have downloaded vhdl files for loopback in the fpga.No changes are done in slave.c firmware and vhdl files except pins assignment.
----------------------------------
Problem:1 (for LOOPBACK example )
----------------------------------
1) when i bulkout hex "01" 512 bytes using Cypress USB Console app,result in bulkin is "02" 512 bytes. correct result.
2) when i bulkout hex "02" 512 bytes using Cypress USB Console app,result in bulkin is "03" 512 bytes. correct result.
....... and so on for bulkouts 03,04,05,06,08,09,0A,0B....and any input which exclude "07" or "0F" i got correct result but
3) when i bulkout hex "07" 512 bytes using Cypress USB Console app,result in bulkin is strange :
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
4) when i bulkout hex "17" 512 bytes using Cypress USB Console app,result in bulkin is " 10 20 "( replace " 00 10 " with "10 20" in above output representation) incorrect result
5) when i bulkout hex "27" 512 bytes using Cypress USB Console app,result in bulkin is " 20 30 "( replace " 00 10 " with "20 30" in above output representation)incorrect result
6) when i bulkout hex "37" 512 bytes using Cypress USB Console app,result in bulkin is " 30 40 "( replace " 00 10 " with "30 40" in above output representation)incorrect result
7) when i bulkout hex "47" 512 bytes using Cypress USB Console app,result in bulkin is " 40 50 "( replace " 00 10 " with "40 50" in above output representation)incorrect result
and so on in same manner up "97".
😎 when i bulkout hex "0F" 512 bytes using Cypress USB Console app,result in bulkin is " 08 18 "( replace " 00 10 " with "08 18" in above output representation) incorrect result
---------------------------------------
Problem 2 : (for STREAMIN example 😞
---------------------------------------
i have downloaded vhdl files of streamin example in fpga and result is not correct ON BULK IN :
08 09 0A 0B 0C 0D 0E 0F 08 09 0A 0B 0C 0D 0E 0F
18 19 1A 1B 1C 1D 1E 1F 18 19 1A 1B 1C 1D 1E 1F
28 29 2A 2B 2C 2D 2E 2F 28 29 2A 2B 2C 2D 2E 2F
38 39 3A 3B 3C 3D 3E 3F 38 39 3A 3B 3C 3D 3E 3F
48 49 4A 4B 4C 4D 4E 4F 48 49 4A 4B 4C 4D 4E 4F
58 59 5A 5B 5C 5D 5E 5F 58 59 5A 5B 5C 5D 5E 5F
68 69 6A 6B 6C 6D 6E 6F 68 69 6A 6B 6C 6D 6E 6F
78 79 7A 7B 7C 7D 7E 7F 78 79 7A 7B 7C 7D 7E 7f
88 89 8A 8B 8C 8D 8E 8F 88 89 8A 8B 8C 8D 8E 8F
98 99 9A 9B 9C 9D 9E 9F 98 99 9A 9B 9C 9D 9E 9F
A8 A9 AA AB AC AD AE AF A8 A9 AA AB AC AD AE AF
B8 B9 BA BB BC BD BE BF B8 B9 BA BB BC BD BE BF
C8 C9 CA CB CC CD CE CF C8 C9 CA CB CC CD CE CF
D8 D9 DA DB DC DD DE DF D8 D9 DA DB DC DD DE DF
E8 E9 EA EB EC ED EE EF E8 E9 EA EB EC ED EE EF
F8 F9 FA FB FC FD FE FF F8 F9 FA FB FC FD FE FF
08 09 0A 0B 0C 0D 0E 0F 08 09 0A 0B 0C 0D 0E 0F
18 19 1A 1B 1C 1D 1E 1F 18 19 1A 1B 1C 1D 1E 1F
28 29 2A 2B 2C 2D 2E 2F 28 29 2A 2B 2C 2D 2E 2F
38 39 3A 3B 3C 3D 3E 3F 38 39 3A 3B 3C 3D 3E 3F
48 49 4A 4B 4C 4D 4E 4F 48 49 4A 4B 4C 4D 4E 4F
58 59 5A 5B 5C 5D 5E 5F 58 59 5A 5B 5C 5D 5E 5F
68 69 6A 6B 6C 6D 6E 6F 68 69 6A 6B 6C 6D 6E 6F
78 79 7A 7B 7C 7D 7E 7F 78 79 7A 7B 7C 7D 7E 7f
88 89 8A 8B 8C 8D 8E 8F 88 89 8A 8B 8C 8D 8E 8F
98 99 9A 9B 9C 9D 9E 9F 98 99 9A 9B 9C 9D 9E 9F
A8 A9 AA AB AC AD AE AF A8 A9 AA AB AC AD AE AF
B8 B9 BA BB BC BD BE BF B8 B9 BA BB BC BD BE BF
C8 C9 CA CB CC CD CE CF C8 C9 CA CB CC CD CE CF
D8 D9 DA DB DC DD DE DF D8 D9 DA DB DC DD DE DF
E8 E9 EA EB EC ED EE EF E8 E9 EA EB EC ED EE EF
F8 F9 FA FB FC FD FE FF F8 F9 FA FB FC FD FE FF
No changes are done in the vhdl and fx2lp firmware.Same files work correctly on the development kit hardware but when i implement these files on my own
hardware, the strange result is above for both examples...!
--------------
QUESTIONS:
--------------
1) the problem which comes in loopback when input containig hex 7 or F. According to my observations of the above outputs, FD.3 data line gives zero instead of '1' at the bulkin when bulkout has
combination containig 7 or F ? Also note the streamin output which is giving 1 at FD.3 line ?
2)what can be the possible problem? FD[7:0] are correctly connected to fpga.
3) is this a hardware issue or software ?
plz help.
thanks
I have three identical FX2LP boards, one of which works fine, the other two fail to enumerate. Has anyone got any hints for things I can try (hardware and/or software) to discover what's up?
The working board enumerates like this: http://pastebin.com/raw.php?i=RApTG5E8
The non-working boards are detected as high-speed devices: http://pastebin.com/ND0HQuW9
...but fail to respond to the host's descriptor requests: http://pastebin.com/raw.php?i=gy2EY0nh
The hardware is pretty minimal:
1) 56-pin SSOP CY68013A (1st bad board) and CY68014A (2nd bad board)
2) D+, D- & GND connected to USB
3) Reset circuit: 22nF capacitor charged through 100K resistor
4) Clock circuit: 24MHz crystal and a pair of 22pF capacitros
5) Two 22nF decoupling capacitors
6) External 3.3V PSU
7) Everything else unconnected (for now)
Show Less
hi,
i am using FX2lP 56-pin package.
I have implemented loopback and streamin examples from the AN61345 . Spartan3E FPGA and fx2lp configuration is done according to the AN61345 .
slave.c is downloaded successfully in the eeprom and detected on Cypress USB Console.
i have downloaded vhdl files for loopback in the fpga.No changes are done in slave.c firmware and vhdl files except pins assignment.
----------------------------------
Problem:1 (for LOOPBACK example )
----------------------------------
1) when i bulkout hex "01" 512 bytes using Cypress USB Console app,result in bulkin is "02" 512 bytes. correct result.
2) when i bulkout hex "02" 512 bytes using Cypress USB Console app,result in bulkin is "03" 512 bytes. correct result.
....... and so on for bulkouts 03,04,05,06,08,09,0A,0B....and any input which exclude "07" or "0F" i got correct result but
3) when i bulkout hex "07" 512 bytes using Cypress USB Console app,result in bulkin is strange :
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
4) when i bulkout hex "17" 512 bytes using Cypress USB Console app,result in bulkin is " 10 20 "( replace " 00 10 " with "10 20" in above output representation) incorrect result
5) when i bulkout hex "27" 512 bytes using Cypress USB Console app,result in bulkin is " 20 30 "( replace " 00 10 " with "20 30" in above output representation)incorrect result
6) when i bulkout hex "37" 512 bytes using Cypress USB Console app,result in bulkin is " 30 40 "( replace " 00 10 " with "30 40" in above output representation)incorrect result
7) when i bulkout hex "47" 512 bytes using Cypress USB Console app,result in bulkin is " 40 50 "( replace " 00 10 " with "40 50" in above output representation)incorrect result
and so on in same manner up "97".
😎 when i bulkout hex "0F" 512 bytes using Cypress USB Console app,result in bulkin is " 08 18 "( replace " 00 10 " with "08 18" in above output representation) incorrect result
---------------------------------------
Problem 2 : (for STREAMIN example 😞
---------------------------------------
i have downloaded vhdl files of streamin example in fpga and result is not correct ON BULK IN :
08 09 0A 0B 0C 0D 0E 0F 08 09 0A 0B 0C 0D 0E 0F
18 19 1A 1B 1C 1D 1E 1F 18 19 1A 1B 1C 1D 1E 1F
28 29 2A 2B 2C 2D 2E 2F 28 29 2A 2B 2C 2D 2E 2F
38 39 3A 3B 3C 3D 3E 3F 38 39 3A 3B 3C 3D 3E 3F
48 49 4A 4B 4C 4D 4E 4F 48 49 4A 4B 4C 4D 4E 4F
58 59 5A 5B 5C 5D 5E 5F 58 59 5A 5B 5C 5D 5E 5F
68 69 6A 6B 6C 6D 6E 6F 68 69 6A 6B 6C 6D 6E 6F
78 79 7A 7B 7C 7D 7E 7F 78 79 7A 7B 7C 7D 7E 7f
88 89 8A 8B 8C 8D 8E 8F 88 89 8A 8B 8C 8D 8E 8F
98 99 9A 9B 9C 9D 9E 9F 98 99 9A 9B 9C 9D 9E 9F
A8 A9 AA AB AC AD AE AF A8 A9 AA AB AC AD AE AF
B8 B9 BA BB BC BD BE BF B8 B9 BA BB BC BD BE BF
C8 C9 CA CB CC CD CE CF C8 C9 CA CB CC CD CE CF
D8 D9 DA DB DC DD DE DF D8 D9 DA DB DC DD DE DF
E8 E9 EA EB EC ED EE EF E8 E9 EA EB EC ED EE EF
F8 F9 FA FB FC FD FE FF F8 F9 FA FB FC FD FE FF
08 09 0A 0B 0C 0D 0E 0F 08 09 0A 0B 0C 0D 0E 0F
18 19 1A 1B 1C 1D 1E 1F 18 19 1A 1B 1C 1D 1E 1F
28 29 2A 2B 2C 2D 2E 2F 28 29 2A 2B 2C 2D 2E 2F
38 39 3A 3B 3C 3D 3E 3F 38 39 3A 3B 3C 3D 3E 3F
48 49 4A 4B 4C 4D 4E 4F 48 49 4A 4B 4C 4D 4E 4F
58 59 5A 5B 5C 5D 5E 5F 58 59 5A 5B 5C 5D 5E 5F
68 69 6A 6B 6C 6D 6E 6F 68 69 6A 6B 6C 6D 6E 6F
78 79 7A 7B 7C 7D 7E 7F 78 79 7A 7B 7C 7D 7E 7f
88 89 8A 8B 8C 8D 8E 8F 88 89 8A 8B 8C 8D 8E 8F
98 99 9A 9B 9C 9D 9E 9F 98 99 9A 9B 9C 9D 9E 9F
A8 A9 AA AB AC AD AE AF A8 A9 AA AB AC AD AE AF
B8 B9 BA BB BC BD BE BF B8 B9 BA BB BC BD BE BF
C8 C9 CA CB CC CD CE CF C8 C9 CA CB CC CD CE CF
D8 D9 DA DB DC DD DE DF D8 D9 DA DB DC DD DE DF
E8 E9 EA EB EC ED EE EF E8 E9 EA EB EC ED EE EF
F8 F9 FA FB FC FD FE FF F8 F9 FA FB FC FD FE FF
No changes are done in the vhdl and fx2lp firmware.Same files work correctly on the development kit hardware but when i implement these files on my own
hardware, the strange result is above for both examples...!
--------------
QUESTIONS:
--------------
1) the problem which comes in loopback when input containig hex 7 or F. According to my observations of the above outputs, FD.3 data line gives zero instead of '1' at the bulkin when bulkout has
combination containig 7 or F ? Also note the streamin output which is giving 1 at FD.3 line ?
2)what can be the possible problem? FD[7:0] are correctly connected to fpga.
3) is this a hardware issue or software ?
plz help.
thanks