USB low-full-high speed peripherals Forum Discussions

Hello,

i am using c2 load eeprom booting for fx2lp in my project.defaulty i2c speed is 100khz.i have red  that it can be 400khz speed by setting the EEPROM Configuration Byte.if 400khz bo bit is one,then it will be 400khz,if its is 0,its 100khz.

but how to make changes ?and where i will find this bit in the fx2lp firmware?let me know.

b7      b6            b5  b4   b3  b2  b1      b0

0    DISCON       0    0     0    0    0    400KHZ

regards,

My apology for writing in Japanese.

Device:CY7C68013A-56PVXCT(FX2LP)

This is a continuation of my previous CDC.
https://community.cypress.com/thread/34347

■質問
上記スレッドにて、FX2LP内蔵のI2CによりFPGAはEP0を読み出す
ことが可能との情報を得ました。
I2CでEP0を読み出すためのシーケンスについて記載された資料はございますか？

■補足
テクニカルリファレンスマニュアル等を確認しておりますが、実際に
I2Cでの読み出しを実施する場合に参考となる情報を見つけることが
出来ませんでした。

I2CであればEP0を読み出せることは、資料に明記されているのでしょうか？

- EZ-USB® Technical Reference Manual
http://www.cypress.com/file/126446/download

Hi,

I am interfaced fx2lp with image sensor in slavefifo mode.sensor is in video stream mode.I have modified cypress control center to recieve the video.first i am writting the fx2lp values in the files.after this displaying video in the display in the host.control center display stops after certain time.

anyone know why this is happening?

thanks,

geethanjali.

Hello,

how to build release version in keil2 in fx2lp?

let me know the procedure for this.

thank you.

I checked Application note, #001-58764 Rev. *I.

http://www.cypress.com/file/44471/download

My apology for writing in Japanese.
Device:CY7C68013A-56PVXCT(FX2LP)

USB CDC(Communication Device Class)の構成例として上記アプリケーションノートを参照しています。
なお、現在検討中のハードウェア構成は次の通りです。
   PC - FX2LP - FPGA

■質問
FPGAに対し、Abstract Control Model Requestを通知する事は可能か。

■補足
Abstract Control ModelはCDC規格のサブクラスの一つで、仮想COM

ポートのエニュメレーションに使用するModelと認識しています。

Abstract Control Model RequestsをFPGAが取得するためにはエンド

ポイント0がFIFOバス経由で読める事が必要かと考えていますが、現状

ではそれは不可能と認識しております。
（この点は、下記の別スレッドで確認させていただきました）
https://community.cypress.com/thread/34294

何らかの方法でFPGAにAbstract Control Model Requestを通知する

手法がございましたらご教授ください。

Hello,

I have interfaced image sensor to fx2lp in slavefifo mode and for this,i have modified control center to display the image in the pc side.image sensor is 752x480 resolution with 60 frames per second.what ever the image frame is displaying in the pc is shifting,that means first frame(partial) is displaying with second frame(partial) in the dispaly.

why it is happening?is it because of data loss?fx2lp and windows are not in sync?how can i solve this problem?i have attached the image display.

help me.

I checked document, #001-13670 EZ-USB Technical Reference Manual.
http://www.cypress.com/file/126446/download

I am question about Figure 9-1 at see page 99.

Question:
Could you tell me FPGA can read data from the CPU EP0?
I understand for readable EPx is EP2, EP4, EP6, EP8.

Best Regards.

Hello everyone ,

                          We are working on FX2LP ,as of now we are using control center for windows application , and its working fine. Further we are looking forward to develop control center and streamer for android applications, is there any source code for android applications.

I hope if someone helps it will be helpful for us.

Thanks And Best Regards

Veerendra

G'morning,

I am hoping that FX2LP can sample a 38kHz signal. It looks like Timer2 is the only one with its own capture register.

Has anyone here successfully received IR using this part?

TIA