USB low-full-high speed peripherals Forum Discussions
3.16 CY_CALLBACK_EVENTS
Enumeration defining UART/SPI transfer error or status bit maps.
Description
Enumeration lists the bit maps that are used to report error or status during UART/SPI transfer.
Members
Members Description
CY_UART_CTS_BIT = 0x01 CTS pin notification bit
CY_UART_DSR_BIT = 0x02 State of transmission carrier. This signal corresponds to V.24 signal 106 andRS-232 signal DSR.
CY_UART_BREAK_BIT = 0x04 State of break detection mechanism of the device
CY_UART_RING_SIGNAL_BIT = 0x08 State of ring signal detection of the device
CY_UART_FRAME_ERROR_BIT = 0x10 A framing error has occurred
CY_UART_PARITY_ERROR_BIT = 0x20 A parity error has occured
CY_UART_DATA_OVERRUN_BIT= 0x40 Received data has been discarded due to overrun in the device
CY_UART_DCD_BIT = 0x100 State of receiver carrier detection mechanism of device. This signal corresponds to V.24 signal 109 and RS-232 signal DCD
CY_SPI_TX_UNDERFLOW_BIT = 0x200 Notification sent when SPI fifo is empty
CY_SPI_BUS_ERROR_BIT = 0x400 Spi bus error has been detected
CY_ERROR_EVENT_FAILED_BIT = 0x800 Event thread failed
Question: How can I read these bits directly? Do you have a DLL to allow me to do that?
Show LessHi,
We plan to use CY7C65211 as SPI master, and CY15B104Q (FRAM) as slave.
Regarding the description of CY7C65211 and CY15B104Q datasheet;
- CY7C65211 SPI master spec : Thmo (hold time) is 0ns min.
- CY15B104Q SPI slave spec : tH (Data hold time) is 5ns min. (VDD=2.7 to 3.6V)
* Both of configuration are CPOL=0 (Mode0)
Is communication specs out of range in this configuration?
In the CY7C65211 output the SCK and Valid data to slave with no hold time, but CY15B104Q can not latch correctly due to hold time is insufficient.
I’m afraid that valid data sent by host but can not be received correctly by slave.
Is my understanding correct?
Best regards, Shohei
Show LessHello,
I have interfaced fx2lp with image sensor in slavefifo configuration.
in AN61345 ,they have given that "The interface clock (IFCLK) coming from the FPGA is shifted by 180 degrees to meet the setup time requirements of the Slave FIFO interface of FX2LP"
I dint understand the above statement.can you please explain?
and i am facing some timimg issues in my appliation?is it above statement maaters when i am using sensor instead of fpga?
regards,
geetha.
Show LessHello,
I have interfaced fx2lp with sensor.sensor is sending one frame at one transfer in click.we are displaying one frame(360960bytes) in the windows side.but image is displaying as attached snap.why this splitting of image is happening even sensor sends only one frame?
regards,
geetha.
Show LessI followed CyUSB3.pdf to add my own VID/PID pair to CyUSB3.inf file.
I did the following, none of them work. No changes to CyUSB3.sys and CyUSB3.cat
1. Add my VID/PID to the .inf and change the strings. Remove all build in PID/VID and the strings, Keep the file name as CyUSB3.inf.
But it never get work. The windows10 (64bits) always shows
2. Only add my VID/PID and strings, without changing any original data in cyusb3.inf. it can install successfully.
note: I have disable my computer Digital Signature.
Can tell me the difference is there?
Thank you.
Show LessHello,
I'm working with an EZ-USB FX3 development kit, connected to a Windows 7 64-bit machine, running my dll which uses the cyapi.lib library. My question is specifically to a failure with the XferData() method on the bulk-out endpoint.
My dll initializes the board (where the FX3 is connected) and programs both the RAM (.img file via CCyFX3Device.DownloadFw) and the FPGA (.bin file via BuilkOutEndPt.XferData) firmware; those two files are our own code. This board is connected to a windows 7 machine and both receive power to be turned on at the same time. After windows startup, I run my dll and the XferData() fails with error 997 (after checking LastError). This error is also seen even if Reset() and Abort() are issued before using XferData. However, if the board is NOT connected to the computer during startup, and then the board is turn on and plug in after windows is ready, everything works just fine (ie. no errors at all).
This behavior is really, really weird since it seems to be connected somehow to the windows startup sequence. We have also tried using a Windows 10 64-bit machine but with the same results.
If anybody has any ideas why we are seeing this error at startup only, or knows how to fix it, please let us know! We'd really appreciate any help.
Thanks,
-Stalin
Show LessI'm trying to use USB2.0 Camera Interface Using FX2LP™ and Lattice CrossLink FPGA - KBA222479 firmware with a Lcsoft CY7C68013A Mini Board connected to my existing FPGA design. I have the firmware uploaded, and the board is recognized as a generic USB video device. I'm specifically only trying to stream data into the FX2LP. I'm trying to figure out:
1. Specifically, what are the minimal set of pins on the CY7C68013A board need to be connected to the FPGA?
2. Which pins are active high/low and how will each pin need to be driven?
FX2LP
PIN A.K.A. Description
PA0 INT0# ??
PA1 INT1# ??
PA2 SLOE This is the enable signal for the FIFO's output driver.
PA3 WU2 ??
PA4 FIFOADR0 These signals select the active endpoint.
PA5 FIFOADR1 These signals select the active endpoint.
PA6 PKTEND ??
CTL0 FLAGA These flags are used by the FIFO to indicate status (Full, Empty,and Programmable)
CTL1 FLAGB These flags are used by the FIFO to indicate status (Full, Empty,and Programmable)
CTL2 FLAGC These flags are used by the FIFO to indicate status (Full, Empty,and Programmable)
PA7 FLAGD FIFO Full flag output from FX2LP. Active low
?? Sync (PC0 of FX2LP) ????
RDY0 SLRD SLRD pin should be asserted by the master to read data from the FIFO
RDY1 SLWR SLWR pin should be asserted by the master to write data to the FIFO.
IFCLK IFCLK 48Mhz clock to FX2LP
PB[0:7] FD[0:7] Lower 8 bits of 16-bit data bus.
PD[0:7] FD[8:15] Upper 8 bits of 16-bit data bus.
1. What is PA0/INT0 used for and is it active high or active low?
2. What is PA1/INT1 used for and is it active high or active low?
3. Is PA2/SLOE active high or active low?
4. Does FIFOADR[0:1] always need to be "10" for my scenario, or "11"? Is it for some reason active low?
5. When does PKTEND need to be asserted and is it active high or active low?
6. What specifically are FLAGA, FLAGB, FLAGC for, and are they active high or active low?
7. What pin is "Sync" on the FX2LP? Is it active high or active low? ( Pin diagram on page 22 https://www.cypress.com/file/138911/download )
8. Can you confirm that SLRD and SLWR are active low?
I've already looked at these references:
USB2.0 Camera Interface Using FX2LP™ and Lattice CrossLink FPGA - KBA222479
https://www.cypress.com/file/44551/download
https://www.cypress.com/file/138911/download
http://blog.malcom.pl/wp-content/uploads/2015/02/CY7C68013A_schematic.png
Thanks
Show LessWe sell several devices which uses Cyprus USB FX2 chips. We have always used the CyUSB.sys driver (which we signed ourselves) but are now running into problems installing these drivers on Windows 10. The upshot is that we need to migrate to using CyUSB3.sys and get the drivers properly signed by Microsoft. I have looked at the ‘Driver Resell’ information and am in the process of generating the necessary information.
I have a question regarding CyUSB3 driver installation (as I was not the developer who developed the CyUSB communications):
At the moment we install specific “.spt” configuration/firmware files at the same time as we install the CyUSB3.sys driver. These files are (very occasionally) updated during product improvements. Is it necessary for us to include these in the CyUSB3 driver installation? If so then would changing the file invalidate the driver certification (assuming the driver already installed)?
Show LessHello!
A few years ago, I wrote an C++ application for Windows - use CY68013, CyAPI-based, and it work good.
And now, after migrating from Visual Studio 2015 to Visual Studio 2017, my application (for CY68013, CyAPI-based) can not build anymore!
I've got the error message:
1>CyAPI.lib(CyAPI.obj) : error LNK2019: unresolved external symbol _sprintf referenced in function "public: void __thiscall CCyUSBDevice::UsbdStatusString(unsigned long,char *)" (?UsbdStatusString@CCyUSBDevice@@QAEXKPAD@Z)
It seems that problem is into CyAPI.lib.
How can I fix it?
Thnx.
Show Less