I am working with the FX2lp / GPIF and go through the AN57322 (Interfacing SRAM with FX2LP over GPIF)
I wonder about the sequenze "within" a decision point / data action point.
- When will be the databus sampled, either for a read waveform or a write waveform within an IFCLK (rising / falling edge) ?
- When will be the control signals set within an IFCLK ( after/before sampling, rising / falling edge) ?
- When will be the RDY singals be sampled, either asynchrounous (SAS= 0) or synchronous(SAS = 1) within a IFCLK ?
- When will be the logical funtion within a DP finally be executed?
What is the "internal delay" between all the sampling and signal settings?
Getting a better understanding within one IFCLK period, can I assume that IFCLK will be a kind of "trippled" for the sampling, setting CTL signals and following logical functions.
Especially for FIFO waveforms (repeating decision points) this is difficult to understand.
Solved! Go to Solution.
- GPIF timing
thanks for your replay.
I`ve gone through the TRM and other application notes, GPIF primer already, but I don`t find explizit answers to my questions. Would you please provide detailed page numbers to look at?
Apologies for the delay in my response.
Can you please check Page 129, Decision Point States in the TRM?