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Hello!
I transfer data from 68013A to cpld, using the synchronous salve fifo mode, and the data bus is 16 bit, but I can only read the first word correctly, and the second word is always the same as the first word, please help me!
the next is my code.
the 68013A code:
void TD_Init( void )
{ // Called once at startup
CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation
REVCTL = 0x01; // MUST set REVCTL.0 and REVCTL.1 to 1
SYNCDELAY;
IFCONFIG = 0x43; //%Slave FIFO接口模式 采用外部时钟 极性正常 内部时钟输出无效 同步操作
//%端点2配置,OUT,双缓冲,BULK 批量输出 数据从PC机到68013
//0xA0 四缓冲 0xA2 双缓冲 0xA3 三缓冲
SYNCDELAY;
EP2CFG = 0xA2; SYNCDELAY;// EP2OUT, bulk, size 512, 2 buffered 命令输出
EP4CFG = 0x02; SYNCDELAY;// EP4 not valid
EP6CFG = 0xe2; SYNCDELAY;// EP6IN, bulk, size 512, 2 buffered 数据输入
EP8CFG = 0x02; SYNCDELAY;// EP8 not valid
//在复位端点FIFO 时,为了保证复位正常,防止主控器请求的干扰,先写入 0x80,然后复位端点,最后写入0x00,使能响应请求。
FIFORESET = 0x80; SYNCDELAY; // activate NAK-ALL to avoid race conditions
FIFORESET = 0x02; SYNCDELAY; // reset, FIFO 2
FIFORESET = 0x04; SYNCDELAY; // reset, FIFO 4
FIFORESET = 0x06; SYNCDELAY; // reset, FIFO 6
FIFORESET = 0x08; SYNCDELAY; // reset, FIFO 8
FIFORESET = 0x00; SYNCDELAY; // deactivate NAK-ALL
//0x11 /16位数据宽度 数据自动提交
EP2FIFOCFG = 0x01; SYNCDELAY;
EP2FIFOCFG = 0x11; SYNCDELAY; //AUTOOUT=1, WORDWIDE=1 16位数据宽度
//16位数据宽度,数据自动提交,可以提交0长度数据封包
EP6FIFOCFG = 0x0D; SYNCDELAY; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1
//%引脚FLAGC、FLAGB、FLAGC、FLAGB配置
PINFLAGSAB = 0x00; SYNCDELAY; // FLAGB - Indexed 满标志低电平有效
PINFLAGSCD = 0x00; SYNCDELAY; // FLAGC - Indexed 空标志低电平有效
//%PKEND\SLOE\SLRD\SLWR 高电平有效 空满标志低电平有效 PKTEND高电平有效,不允许短包
FIFOPINPOLAR = 0x3C; SYNCDELAY; // FLAGB/A 读写和使能 高有效
EP6AUTOINLENH = 0x02; SYNCDELAY;
EP6AUTOINLENL = 0x00; SYNCDELAY; //端点6数据包长度512
OEA |= 0x0B;
IOA &= 0xF4;
}
The following is the cpld code:
assign usbifclk = clk;
always @(negedge clk)
begin
if(!rst)
begin
present_state <= state_idel;
count_clk <= 10'd0;
slrd <= 1'b0;//slrd and sloe is 1 active
sloe <= 1'b0;
config_done <= 1'b0;
done_delay_cnt <= 3'd0;
user_control_data <= 20'd0;
end
else
begin
case(present_state)
state_idel :
begin
if((!usbfifo_full)&(usbfifo_empty))
begin
present_state <= state_read;
slrd <= 1'b1;
sloe <= 1'b1;
end
else if((!usbfifo_empty)&(usbfifo_full))
begin
present_state <= state_idel;
slrd <= 1'b0;
sloe <= 1'b0;
end
end
state_read :
begin
if(count_clk <= 10'd511)
begin
count_clk <= count_clk + 1'b1;
if(count_clk == 10'd511)
begin
slrd <= 1'b0;
sloe <= 1'b0;
end
else
begin
slrd <= 1'b1;
sloe <= 1'b1;
end
if(count_clk == 10'd0)
user_control_data[15:0] <= fddata;
else if(count_clk == 10'd1)
user_control_data[19:16] <= fddata[3:0];
end
else if(count_clk == 10'd512)
begin
count_clk <= 10'd0;
config_done <= 1'b1;
present_state <= state_delay;
end
end
state_delay :
begin
if(done_delay_cnt<=3'd6)
done_delay_cnt <= done_delay_cnt + 1'b1;
else
begin
config_done <= 1'b0;
done_delay_cnt <= 3'd0;
present_state <= state_idel;
end
end
default :
present_state <= state_idel;
endcase
end
end
Now, the problem is that: When I send 1024 bytes through fifo2 to cpld, such as {22 2A 0B 01 01 ... 01}, the cpld can run the code and read over the full 1024 bytes, and user_control_data[15:0] is correct(22 2A), but the received user_control_data[19:16] is always the same as the user_control_data[3:0](22), How can I solve the problem? I checked the sequence diagram, the it seems does right.
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Hi,
SYNCDELAY;
EP2CFG = 0xA2; SYNCDELAY;// EP2OUT, bulk, size 512, 2 buffered 命令输出
EP4CFG = 0x02; SYNCDELAY;// EP4 not valid
EP6CFG = 0xe2; SYNCDELAY;// EP6IN, bulk, size 512, 2 buffered 数据输入
EP8CFG = 0x02; SYNCDELAY;// EP8 not valid
this is not valid configuration for endpoints.Pls refer fugre 2.5 of datasheet for valid configuration options
i don't this "user_control_data[19:16] <= fddata[3:0];" What is fddata[3:0]?
Regards,
Vikas