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USB low-full-high speed peripherals Forum Discussions

Anonymous
Not applicable

 Hi

   

I willing to use internal ifclk to clock stable then resetting to external ifclk in FPGA. 

   

But i dont know how am i coding to switching internal ifclk to external ifclk in verilog

   

 

   

Is this need to inout port in verilog for clock switching?

   

Does anyone please let me know some example code for that?

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1 Solution
Anonymous
Not applicable

 dv2

   

Please check out the projects attached with the AN61345.

   

The projects and documentation have been updated.

   

In the App note projects, the switching of clock from internal to external has been implemented.

   

Please go through the App note for better understanding.

   

Thanks

   

Nikhil

View solution in original post

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7 Replies
Anonymous
Not applicable

 dv2

   

Please check out the projects attached with the AN61345.

   

The projects and documentation have been updated.

   

In the App note projects, the switching of clock from internal to external has been implemented.

   

Please go through the App note for better understanding.

   

Thanks

   

Nikhil

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Anonymous
Not applicable

 Thanks A lot

   

I just view updated F/W. It seems like solution for my case. 

   

But i have some questions.

   

1. Now i have running in fx2lp-56pin, can i use "IOA" for instead "IOC"?

   

(are there any change register setting for "IOA"?)

   

2. What am i supposed to make slwr and sensor's hsync signal in verilog during slavefifo?

   

(please verilog example code update please)

   

3.Also in verilog, what am i supposed to make "clock switchin" in verilog during slavefifo?

   

In switching from internal IFCLK to external IFCLK in verilog, what am i supposed to do?

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Anonymous
Not applicable

 dv2

   

If you are not using port A in your application , you can switch IOC with IOA.

   

I am just explaining the flow here for clarity:

   

1) intitially FX2LP is loaded with slave firmaware with IFCLK internal

   

2) FPGA is loaded with bit stream. As soon as FPGA comes up, it pulls "done" pin high

   

If you look at the file "slave.c" of FX2LP project, under function "TD_Poll", the code is written for monitoring PC.1 (PC.1 is onnected to done pin of FPGA), So as soon as PC.1 is high IFCONFIG (register fo rchanging IFCLK) is converted to EXTERNAL CLK and PC.0 pin of FX2LP is made high

   

PC.0 is connected to SYNC pin of FPGA. As soon as SYNC is high FPGA outputs the CLK. This CLK is provided to IFCLK of FX2LP. Inside FPGA, CLK is derived by taking CLKOUT from FX2LP.

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Anonymous
Not applicable

 Is yours a UVC application?

   

Can you please explain a little about your setup/application?

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Anonymous
Not applicable

one of us can comment more on whether hsync is to be connected to slwr  once we get an idea of your application.

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Anonymous
Not applicable

 Could you please let me know more detail? For about  slwr hsync?

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Anonymous
Not applicable

 hsync-slave select/enable

   

vsync-slave write

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