Slavefifo and hsync slwr relationship?

[Anonymous]

 Hi

   

I'm not sure about these relation scheme. 

   

When i using slave fifo, fpga receive hsync from sensor. 

   

But i dont know how should i make slwr with hsync. 

   

Can i just use hsync for instance slwr?  

   

How am i make use hsync in slave fifo in FPGA

   

Could somebody help to me some advice?

[Anonymous]

 Can you please explain if yours is a UVC application?

[Anonymous]

 Usually this is the way line are connected in image sensor application

   

Frame valid - Slave select

   

Line Valid - Slave write

   

Please see if you can use this information.