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USB low-full-high speed peripherals Forum Discussions

AnMc_4628076
Level 1
5 replies posted 5 questions asked 5 sign-ins
Level 1

This question was not quite fully-answered...for my application, I have a mux setup for multiple SPI devices. 

Specifically: I need to know the minimum time from SSEL_OUT assertion (going low) to start of the SPI master clock action.

Thanks.

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YatheeshD_36
Moderator
Moderator 750 replies posted 500 replies posted 250 solutions authored
Moderator

Hello,

In SPI master mode, the SSEL assertion to SCLK timing is not fixed, It varies with frequency.

At higher Clock frequencies, the time difference between SPI SSEL assertion and SCLK will reduce.

At 2MHz frequency the difference between SS and SCLK it is found to be around 1us, both at the start and end of transfer.

Please let me know the USB-Serial SPI master clock frequency you will be using?

Thanks,

Yatheesh  

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YatheeshD_36
Moderator
Moderator 750 replies posted 500 replies posted 250 solutions authored
Moderator

Hello,

In SPI master mode, the SSEL assertion to SCLK timing is not fixed, It varies with frequency.

At higher Clock frequencies, the time difference between SPI SSEL assertion and SCLK will reduce.

At 2MHz frequency the difference between SS and SCLK it is found to be around 1us, both at the start and end of transfer.

Please let me know the USB-Serial SPI master clock frequency you will be using?

Thanks,

Yatheesh  

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