This IC is used as a master to transmit data to a slave microcontroller via SPI communication.
SPI communication is used to send data to the slave microcontrollers.
However, the output time of this IC is less than half of the clock time.
It is difficult to satisfy the AC timing (hold time) between the slave microcontroller and the receiver microcontroller.
We are having a hard time satisfying the AC timing (hold time) between the slave microcontroller and the receiver microcontroller.
In the data sheet of this IC, "Figure 1.SPI Master Timing" in the datasheet of this IC.
In the time chart of SPI Master Timing for CPHA = 0, MOSI(output) is output on the falling edge of SCK and
The output ends at the rising edge of SCK.
Therefore, the hold time is 0ns (THMO = 0ns).
Is this timing correct for data output?
Is data not output during one cycle from the falling edge of SCK to the falling edge of the next cycle?
(although in slave mode, one cycle of data retention is requested from the other side).
Regarding question 1, if there is no mistake in the timing on the data sheet, the actual measurement of the data appears to show that the data changes with each falling edge of SCK.(every cycle).
This means that if the output is OFF at half-clock on SCK, the remaining half-wave is The high input impedance of the microcontroller on the receiver Is it correct to think that the potential is held by the capacitive component of the circuit? Is this correct?
In relation to question 2 above, even after the output gate is turned off, does the output have an internal structure that keeps the potential for a while?
(How many pF is the output capacitance of this IC terminal?
Kindly refer to the following KBA: https://community.infineon.com/t5/Knowledge-Base-Articles/PSoC-4-SCB-SPI-bus-timing-test-KBA233619/t...
Although it is for a different device, the SPI bus timing is explained.
Thank you for your answer.
I have confirmed KBA. But my question has not been resolved yet.
I expected the timings shown in KBA's "Figure 1. SPI Component Timings"
(Mode 0: CPOL is '0', CPHA is '0':), but In your CY7C65211A datasheet (page 11/37)
"SPI Master Timing for CPHA = 0" (CPOL = 0), the MOSI(output) timing is turned off at the rising edge of the clock. (The timing is different from KBA)
This is why I am asking the question in my previous email.
Once again, please respond to Q1 through Q3 of my previous email.
I have an additional question.
I am trying to send data to a slave device using this IC as a master.
In the CY7C65211A datasheet (page 11/37) "SPI Master Timing for CPHA = 0" (CPOL = 0),
In this case, this IC is the master and outputs data, so I think the waveform on the MOSI(output) side of the data sheet is applicable.
Or, does MOSI(output) mean when this IC receives data?
(Does SPI master mean that the other side is the master?)
When this IC is the master, it is recognized that data output is turned off at the rising edge of
SCK (CPOL=0). Is this correct?
Apologies for the delay in response.
The figure you are pointing to in the datasheet corresponds to the case when the IC is used as SPI Master. So, when CPHA = 0 and CPOL = 0, data is sampled on the rising edge of the clock and shifted on the falling edge of the clock. This is what is depicted in the datasheet.
Thank you for your answer.
However, we have yet to receive an answer to our initial questions.（Q1～3）
I understood that the diagram pointed out in the datasheet shows this IC as a master and MOSI is the output of this IC.
However, in that case, there would be a difference between CY7C65211A and KBA as shown in the attached figure.
I have sent you the first three questions to confirm the specifications of this difference, and I would appreciate an answer to each of them as soon as possible.