How to use the external clock to write to the CY7C68013A?

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Anonymous
Not applicable

 I use the FPGA to generate the clock for communicating with the CY7C68013A with the same code which is usable in the internal clock . But with the external clock , FPGA can not write the data to the FIFO of the CY7C68013A anymore. The flag of empty is always low. I do not know which part of the system is wrong , can you give me some advice?

   

Thanks.

   

kong.

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Anonymous
Not applicable

 By the way,  the FPGA can read the data from the CY7C68013 with the external clock which is from the FPGA. The timing of the operation is the same as the TRM. I have tried to reduce the frequency of the ifclk, but it did not work as well.

   

 

   

PS:The firmware program is as follows:

   

 

   

   

 //时钟为48MHz

   

CPUCS=((CPUCS&~bmCLKSPD)|bmCLKSPD1);

   

IFCONFIG=0x43;    //外部时钟,48MHz,Slave FIFO模式,同步传输

   

REVCTL=0x03;    //必须

   

EP1OUTCFG=0xA0;

   

EP1INCFG=0xA0;    //BULK

   

SYNCDELAY;

   

 

   

//配置端点6的工作状态

   

EP6CFG=0xE8;      //4*512,BULK,IN

   

SYNCDELAY;

   

FIFORESET=0x80;   //复位端点寄存器

   

SYNCDELAY;

   

FIFORESET=0x06;    //复位端点6

   

SYNCDELAY;

   

FIFORESET=0x00;  //end reset

   

SYNCDELAY;

   

EP6FIFOCFG=0x0D;    //端点FIFO配置寄存器,8Bits,自动

   

SYNCDELAY;

   

EP6AUTOINLENH=0x02;  //自动提交512字节

   

SYNCDELAY;

   

EP6AUTOINLENL=0x00;    

   

SYNCDELAY;

   

 

   

//端点4和端点8禁止

   

EP4CFG=0x00;

   

SYNCDELAY;

   

EP8CFG=0x00;

   

SYNCDELAY;

   

 

   

//配置端点2的工作状态

   

EP2CFG=0xA0;     //4*512,BULK,OUT

   

SYNCDELAY;

   

FIFORESET=0x80;   //复位端点寄存器

   

SYNCDELAY;

   

FIFORESET=0x02;    //RESET EP2

   

SYNCDELAY;

   

FIFORESET=0x00;    //结束复位过程

   

SYNCDELAY;

   

OUTPKTEND=0x82;

   

SYNCDELAY;

   

OUTPKTEND=0x82;

   

SYNCDELAY;

   

OUTPKTEND=0x82;

   

SYNCDELAY;

   

OUTPKTEND=0x82;

   

SYNCDELAY;

   

EP2FIFOCFG=0x10;    //端点FIFO配置寄存器,8Bits,自动

   

SYNCDELAY;

   

PINFLAGSAB=0x00;    //FLAGA可编程标志位,FLAGB满标志

   

SYNCDELAY;

   

PINFLAGSCD=0x00;     //FLAGC空标志

   

FIFOPINPOLAR=0x00;    //低电平有效

   

SYNCDELAY;

   

PORTACFG=0x00;

   

OEA=OEA|0x80;

   

IOA=IOA|0x80;

   

EP6FIFOPFH=0x80;

   

SYNCDELAY;

   

EP6FIFOPFL=0x00;

   

SYNCDELAY;

   

EP2BCL=0x80;

   

SYNCDELAY;

   

EP2BCL=0x80;

   

SYNCDELAY;

   

EP2BCL=0x80;

   

SYNCDELAY;

   

EP2BCL=0x80;

   

SYNCDELAY;

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Anonymous
Not applicable

 By the way,  the FPGA can read the data from the CY7C68013 with the external clock which is from the FPGA. The timing of the operation is the same as the TRM. I have tried to reduce the frequency of the ifclk, but it did not work as well.

   

 

   

PS:The firmware program is as follows:

   

 

   

   

 //时钟为48MHz

   

CPUCS=((CPUCS&~bmCLKSPD)|bmCLKSPD1);

   

IFCONFIG=0x43;    //外部时钟,48MHz,Slave FIFO模式,同步传输

   

REVCTL=0x03;    //必须

   

EP1OUTCFG=0xA0;

   

EP1INCFG=0xA0;    //BULK

   

SYNCDELAY;

   

 

   

//配置端点6的工作状态

   

EP6CFG=0xE8;      //4*512,BULK,IN

   

SYNCDELAY;

   

FIFORESET=0x80;   //复位端点寄存器

   

SYNCDELAY;

   

FIFORESET=0x06;    //复位端点6

   

SYNCDELAY;

   

FIFORESET=0x00;  //end reset

   

SYNCDELAY;

   

EP6FIFOCFG=0x0D;    //端点FIFO配置寄存器,8Bits,自动

   

SYNCDELAY;

   

EP6AUTOINLENH=0x02;  //自动提交512字节

   

SYNCDELAY;

   

EP6AUTOINLENL=0x00;    

   

SYNCDELAY;

   

 

   

//端点4和端点8禁止

   

EP4CFG=0x00;

   

SYNCDELAY;

   

EP8CFG=0x00;

   

SYNCDELAY;

   

 

   

//配置端点2的工作状态

   

EP2CFG=0xA0;     //4*512,BULK,OUT

   

SYNCDELAY;

   

FIFORESET=0x80;   //复位端点寄存器

   

SYNCDELAY;

   

FIFORESET=0x02;    //RESET EP2

   

SYNCDELAY;

   

FIFORESET=0x00;    //结束复位过程

   

SYNCDELAY;

   

OUTPKTEND=0x82;

   

SYNCDELAY;

   

OUTPKTEND=0x82;

   

SYNCDELAY;

   

OUTPKTEND=0x82;

   

SYNCDELAY;

   

OUTPKTEND=0x82;

   

SYNCDELAY;

   

EP2FIFOCFG=0x10;    //端点FIFO配置寄存器,8Bits,自动

   

SYNCDELAY;

   

PINFLAGSAB=0x00;    //FLAGA可编程标志位,FLAGB满标志

   

SYNCDELAY;

   

PINFLAGSCD=0x00;     //FLAGC空标志

   

FIFOPINPOLAR=0x00;    //低电平有效

   

SYNCDELAY;

   

PORTACFG=0x00;

   

OEA=OEA|0x80;

   

IOA=IOA|0x80;

   

EP6FIFOPFH=0x80;

   

SYNCDELAY;

   

EP6FIFOPFL=0x00;

   

SYNCDELAY;

   

EP2BCL=0x80;

   

SYNCDELAY;

   

EP2BCL=0x80;

   

SYNCDELAY;

   

EP2BCL=0x80;

   

SYNCDELAY;

   

EP2BCL=0x80;

   

SYNCDELAY;

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Anonymous
Not applicable

 EP6CFG = 0xE8

   

suggests you have configured EP6 as 1024*4 buffered.

   

4K buffering for EP6 is not allowed.

   

Try EP6CFG = 0xE0

   

You can have a look at the slave fifo project associated with AN61345.

   

 

   

Thanks

   

Nikhil

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Anonymous
Not applicable

 I have try to set the EP6CFG = 0xE0,but it still did not work.

   

By the way, I run the FPAG program first to make the clock be set before the firmware was set. So, before the USB start to work, the FPGA has written some signal to the USB. Does it make something wrong with the USB?

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Anonymous
Not applicable

 Can you please explain what do you mean by 'fpga written some signal to USB'?

   

Your setup seems similar to the one explained in AN61345. Did you have a look at that App note?

   

If not please do.

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