- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
HELP!
I'm now using FPGA to generate data, write them in 68013 through the slave fifo interface, initial codes like these:
CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
SYNCDELAY;
REVCTL = 0x03; //ENH_PKD=1, out packets edit-able to the core
SYNCDELAY;
PINFLAGSAB = 0x00 | bmBIT7 | bmBIT6; // FLAGB - EP2FF
SYNCDELAY;
PINFLAGSAB |= bmBIT3; // FLAGA - EP2EF
SYNCDELAY;
PINFLAGSCD = 0x00 | bmBIT2; // FLAGC - EP2PF
SYNCDELAY;
IFCONFIG = 0xE3; // b'1110 0011, FIFO clock source out, 48M, clock output enabled; Slave FIFO mode.
SYNCDELAY;
//EP1 bulk
EP1OUTCFG = 0xA0; //b1=1 Valid; [b5,b4]=1:0, bulk;
SYNCDELAY;
EP1INCFG = 0xA0;
SYNCDELAY;
//// out endpoints do not come up armed. Arm EP1OUT endpoints
EP1OUTBC = 0x40; // arm the EP1 OUT endpoint by writing to the byte count
SYNCDELAY;
EPIE |= bmBIT3; // Enable EP1 OUT Endpoint interrupts
SYNCDELAY;
EPIE |= bmBIT2; // Enable EP1 IN Endpoint interrupts
SYNCDELAY;
// EP4 and EP8 are not used in this implementation...
EP2CFG = 0x00 | bmBIT7 | bmBIT6 | bmBIT5 | bmBIT3; //in buffer 1024 bytes, 4x, bulk
SYNCDELAY;
EP6CFG &= 0x7F; //clear valid bit
SYNCDELAY;
EP4CFG &= 0x7F; //clear valid bit
SYNCDELAY;
EP8CFG &= 0x7F; //clear valid bit
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x82; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;
EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=1,
SYNCDELAY;
// core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's
EP2FIFOCFG = bmBIT0|bmBIT3; // AUTOIN=1(bmBIT3), ZEROLENIN=1(bmBIT2), WORDWIDE=1(bmBIT0)
SYNCDELAY;
EP2AUTOINLENH = 0x00 | bmBIT2; // Packet Length = 1024bytes
SYNCDELAY;
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi
FPGA might be overwritting the buffer when you are sending the the data through RS232 interface.
If you send just 4096 bytes from FPGA(and stop it sending the data afterwards) and if you try to send through UART are you getting correct data?
Regards,
Vikas.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi VAVC, thank you for your post.
But I've tried to turn the AUTOIN mode into Manual mode, and it still can't get the right data. The procedure is like this:
1. Autoin mode, 68013 got data, EP24FIFOFLAGS showed EP2 is full, EP2468STATE showed EP2 is full, EP2CS showed there are 4 packets in buffer.
2. I turn Autoin off, into Manual mode, then I read EP2FIFOBUF data using sentences like this: EP0BUF[0]=EP2FIFOBUF[0]; I use EP0 for debug. I got wrong answer.
3. I use CyConsole->EZ USB Interface to fetch a packet from EP2IN, I got EP24FIFOFLAGS not full not empty, EP2468STATE not full not empty, EP2CS showed there are 3 packets in buffer.
4. Repeat '2', still wrong answer.
5. Repeat '3' till EP24FIFOFLAGS was empty, EP2468STATE was empty, EP2CS showed there are 0 packet in buffer. BUT then it stayed like this, no further packets got in anymore! BUT it should be because in Autoin mode I can get continuous data from FPGA. So the actual EP2EF Pin must not been actived while it should be.
6. I try to reset the fifo using:
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY;
EP2FIFOCFG = 0x00; //switching to manual mode
SYNCDELAY;
FIFORESET = 0x02; // Reset FIFO 2
SYNCDELAY;
EP2FIFOCFG = bmBIT0;
SYNCDELAY;
FIFORESET = 0x00; //Release NAKALL
SYNCDELAY;
BUT still no FPGA data got in!
7. I turn 68013 to AUTOIN mode, data continuously got in again!
So there are basicly two questions:
1. Why I can't get the right EP2FIFOBUF data in my firmware?
2. Why in manual mode the slave fifo interface flags don't change?
PLEASE HELP! I'm going crazy dealing with these problems! Many many thanks!
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ,
Let me explain about AUTOIN and MANUAL,
In AUTOIN mode data is directly commited to USB core. In this CPU doesn't have control over the data.
In Manual mode the data has to be commited by CPU to USB core. Before commiting CPU can edit or even it can skip the data.
You cannot edit data or use that data once it is commited to USB core. If you want to read or edit the data keep it in manual mode and then send data from FPGA , copy the data and then comit the data to USB core
When you are using AUTOIN mode you have to check E2468STAT to know the status of the buffer rather than EP24FIFOFLGS.
Regarding your step 5:
When it is manual mode FPGA can write data into endpoint buffers but HOSt cannot read data from device because the hasn't committed the data to USB core.
Regarding your question 2
2.Why in manual mode the slave fifo interface flags don't change?
A) On what basis you are mentioning that FLAGS are not changing?
As you have configured that EP2 as 1024 bytes buffer change it to 512. please refer the link http://www.cypress.com/?id=4&rID=31675
Also change the AUTOIN length EP2AUTOINLENH to 512 bytes.
Regards,
Vikas.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Vikas, thank you very much for your reply, the infomation is very important for me.
I still have questions, thank you in advance.
A. After step 5 in my previous post, I tried commit/skip packets in firmware, but still got wrong answers, codes are like these: case 0xDE:
{
INPKTEND = 0x02;
SYNCDELAY;
EP0BUF[0]=EP2FIFOBUF[0]; //
SYNCDELAY;
EP0BUF[1]=EP2FIFOBUF[1]; //
SYNCDELAY;
EP0BUF[2]=EP2FIFOBUF[2]; //
SYNCDELAY;
EP0BUF[3]=EP2FIFOBUF[3]; //
SYNCDELAY;
EP0BUF[4]=EP2FIFOBUF[4]; //
SYNCDELAY;
EP0BUF[5]=EP2FIFOBUF[5]; //
SYNCDELAY;
EP0BCL = 6;
SYNCDELAY;
}
break;
case 0xDF:
{
INPKTEND = 0x82;
SYNCDELAY;
SYNCDELAY;
SYNCDELAY;
SYNCDELAY;
EP0BUF[0]=EP2FIFOBUF[0]; //
SYNCDELAY;
EP0BUF[1]=EP2FIFOBUF[1]; //
SYNCDELAY;
EP0BUF[2]=EP2FIFOBUF[2]; //
SYNCDELAY;
EP0BUF[3]=EP2FIFOBUF[3]; //
SYNCDELAY;
EP0BUF[4]=EP2FIFOBUF[4]; //
SYNCDELAY;
EP0BUF[5]=EP2FIFOBUF[5]; //
SYNCDELAY;
EP0BCL = 6;
SYNCDELAY;
}
B. I'm sure that if EP2EF pin was actived then my FPGA would write data into EP2, but why after step '5' the EP24FIFOFLAGS never change? I mean EP24FIFOGLAGS always showed that EP2 was empty? And no matter if I commit or skip packets using codes above the EP24FIFOGLAGS never change either? Of cause EP2468STATE never change as same.
C. About http://www.cypress.com/?id=4&rID=31675: My god it seems I nerver configured EP2 right... I always use 1024byte * 4 buffer...But I also noticed that in CyConsloe->EZUSB Interface, EP2 was recognized as 1024bytes in bulk, and if I press the 'Bulk Trans' button I can get 1024 bytes data. And if my EP2 in full in autoin mode, while I checked that EP2CS had 4 packets, I stoped the FPGA, so no data came further, I can still get 4096 bytes from EP2, not 2048, why?
Thank you!
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Vikas, there's anothor question.
About your post:
"FPGA might be overwritting the buffer when you are sending the the data through RS232 interface."
How could data in slave fifo be overwritten? If I continously writting data from FPGA to 68013 no matter how the slave fifo flags changes, the previous data I've written into 68013 will be overwritten?
I actually configured my FPGA to checkout the slave fifo flags first before souring data into 68013.
Thank you.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi
Regarding your last question, if FPGA doesn't check the FULL flag and if it keep writing into the endpoint buffer then it will rewrtie the data in the buffer.
If you check the FULL flag before writing then there won't be any issue.
Regards,
Vikas.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ,
As you have mentioned that you are getting 4096Bytes, it is not possible fo BULK. Also you have mentioned that EP2 is recognized as BULk 1024bytes. For BULK in high spedd the maximum packet size should not be more than 512 packets.
Can you please share the entire project?zip the project and share it .Use mozilla
Regards,
Vikas.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Vikas, thank you for your reply.
About my previous post relating:
"B. I'm sure that if EP2EF pin was actived then my FPGA would write data into EP2, but why after step '5' the EP24FIFOFLAGS never change? I mean EP24FIFOGLAGS always showed that EP2 was empty? And no matter if I commit or skip packets using codes above the EP24FIFOGLAGS never change either? Of cause EP2468STATE never change as same."
I'm quite confused about that now.
Here's my entire project:
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Vikas, I've uploaded my project using mozilla, but I can't see it, I don't know if you can see it?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
It seems there is no attachment. Please create a tech support case and share the entire project http://www.cypress.com/?id=4&source=header#. One of our engineer will assist you on this issue.
Regards,
Vikas.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi vikas,
I've created a case, no. 2608048169. Please check. Thank you! BTW, could other visitors download my firmware I uploaded? I'd like to keep it unleaked, thank you!
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ,
If you share any thing in the case then other users cannot acces it. It is totally secured. One of our engineer will assist you through the case.
Regards,
Vikas
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Can anybody help me?