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USB low-full-high speed peripherals Forum Discussions

KaRa_4407801
Level 1
Level 1

Hello,

I need to implement a GPIF slave in a Xilinx FPGA. The FPGA will receive the transactions via the TGIF interface and access different Xilinx IPs.

I have 2 questions:

1. Is there a FPGA example design for that?

2. I will need to have a bridge to go from TGIF to AXI, does Cypress has an application note on how to do that?

Thank you,

Kate

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YatheeshD_36
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hello,

Sorry to say that are no example projects where FX2LP is interfaced to FPGA in GPIF mode and AN's explaining configuration on the FPGA side as a slave.

Please refer to AN63620 which uses GPIF to configure the FPGA. Once the FPGA is configured then the mode is switched to slave FIFO mode.

AN61345 implements interface between FX2LP and FPGA where FX2LP is in slave FIFO mode.

AN84868 uses FX3 to configure the Xilinx FPGA using GPIF II.

Best Regards,

Yatheesh

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YatheeshD_36
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hello,

Sorry to say that are no example projects where FX2LP is interfaced to FPGA in GPIF mode and AN's explaining configuration on the FPGA side as a slave.

Please refer to AN63620 which uses GPIF to configure the FPGA. Once the FPGA is configured then the mode is switched to slave FIFO mode.

AN61345 implements interface between FX2LP and FPGA where FX2LP is in slave FIFO mode.

AN84868 uses FX3 to configure the Xilinx FPGA using GPIF II.

Best Regards,

Yatheesh

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Thanks for the info.

So the usual use case that is documented is where the FPGA is the master?

Also, there are no use cases where GPIF is translated to AXI?

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Hello,

FX2LP is mostly used in slave FIFO mode where FPGA acts as a master.

Sorry to say that there are no examples where GPIF is translated to AXI.

Best Regards,

Yatheesh

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