I am wiring up an embedded device to trasmit data via the FX3 to a PC. I'm using pretty much a stock SlaveFifoSync.img from the examples in the development kit, and the GPIF interface. I'm transmitting 16 bits per PCLK toggle.
My data comes from reading a 16-bit ADC. I end up with 2048 ADC reads per data packet, ie 4096 bytes of date per packet.
I figure I *should* be able to just put the data on the data lines, then toggle PCLK to load it, repeat that 2048 times, then terminate the transfer with a PKTEND toggle.
But I lose data. The content is obviously there, but it's not in the right place.
If I add some dummy PCLK toggles, and by some I mean 12 at the front and 88 at the back of each toggle, everything I get lines up nicely, but I end up missing some samples in there.
What I'm thinking is that even though I'm doing a 4096 byte transfer, what's actually happneing is about four 1024 transfers (size of the xmit buffer in the config I have), and that there are some expected header bytes, or possibly some delays that the extra PCLK toggles are making up for.
I have read the documentation, but I'm obviously missing something. Would greatly appreciate input.
What's the DMA buffer size and count in your Fx3 firmware?
And how have you implemented the state machine on the master side? Have you made sure to perform data transfers only when looking at the DMA_RDY flag to determine that there is space to fill in the Fx3?
Since you are using the PKTEND signal at the end of a burst of 2048 clocks, I presume your DMA buffer size is greater than 4096.
In such a case, once you've determined that the buffer is ready to take in data and you start transmitting data using the SLWR signal and driving the data bus from the master, you should be able to receive all the 4096 bytes without any hiccups.
If your buffer size is less than 4096 (you mentioned xmit buffer being 1024, I'm not sure if you meant Fx3 buffer or the buffer on the master), for example 1024, then you will end up switching buffers after every 1024 bytes are filled and this involves a finite delay. If you transmit data during this time, it will be lost.
Apart from that, you can also look at the timing diagrams for sync write operation (available in the datasheet and the AppNote: http://www.cypress.com/?rID=51581) to make sure you're interface meets the required timing spec.
Also, it could be possible that the data loss/mismatch might be happening at the master end itself (maybe you're not driving out the data quickly enough and the buffers are getting rewritten with new data).