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Dear community,
I have a project that need to interface FPGA with USB FX2 via GPIF FIFO read, FX2 then retrieve all valid data and display it in PC.
FPGA sends data to FX2 with corresponding datavalid (READY2) signal.
I have configured the GPIF interface as shown below:
And here is the waveform:
The problem is I always:
+ Missing and the 2 first package(1)
+ Receive redundant package at the end of cycle (2)
because GPIF always checks the condition at the end of the clock cycle (although decision points are placed at the beginning of the state in which they occur, not end).
Here is the FPGA waveform:
I solved (1) by adding 2 clock cycles after asserting CTRL [1: 0] then getting data , it's just a temporary solution. (2) still exists.
Can you please give me the best solution? I just want to get data at signal datavalid (READY2).
Thanks very much!
Best regards,
Ho.
Solved! Go to Solution.
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- GPIF FIFO FPGA FX2
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Hi,
As you see from timing diagram, valid RDY signal should be asserted atleast 9ns (tSRY) before the clock. Please make sure all signals comply with setup and hold times as specified in datasheet.
Pranava
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Hi,
It looks like there is timing issue in RDY signal.
Are you sampling RDY signals synchronously or asynchronously? Can you please specify the GPIFREADYCFG register value you are using in your firmware?
Pranava
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Hi,
I kept the default configuration of GPIFREADYCFG:
After exporting to gpif.c, I found that GPIFREADYCFG register value is 0x00 (I cannot understand this point, where we can change this value in GPIF designer?), then I modified to 0x40 (SAS = 1'b1) and run but no luck!
Please help!
Thanks,
Ho.
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Hi,
GPIFREADYCFG is assigned with the InitData[0] so it is 0xE0 in your code. You need not modify 0x00 to 0x40 as you have done. 0xE0 imply SAS = 1, so it should be sampling synchronously.
Can you please make sure the setup time of RDY signal complies with the Table 18 and Table 19 of the FX2LP datasheet (https://www.cypress.com/file/138911/download)
Pranava
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Hi,
I misunderstood the position of GPIFREADYCFG , so thank you for your comment.
Regarding the setup time of the RDY signal, do you mean the setup time FPGA and FX2LP RDY should match?
Could you please give me your advice on it?
Thank you!
Ho.
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Hi,
As you see from timing diagram, valid RDY signal should be asserted atleast 9ns (tSRY) before the clock. Please make sure all signals comply with setup and hold times as specified in datasheet.
Pranava
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Hi,
Thanks for your suggestion! Is there any way to resolve this from the FX2LP side? Because in the FPGA, valid signals are always accompanied by data, and generating an earlier valid signal is not easy!
Thanks,
Ho.
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Hi,
Updated: I tried to invert IFCLK but no change!
Best regards,
Ho.
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Hi,
There is no other way other than satisfying respective setup times of data and ready signals.
Also you can try to capture waveforms of GSTATE pins to verify the state machine behavior.
If possible please do share your firmware project
Pranava
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Hi,
I changed FPGA code to generate RDY2 one lock earlier and it run properly!
Thank you very much!
Best regards,
Ho.