I am currently working on a project to get the video out of a camera using a FX2LP. I am trying to understand the FIFO read using GPIF. I have attached the FSYNC to RDY0 and LSYNC to RDY1. The hardware seems to work right as i able to receive the data out of the camera using a single read byte. I want to FIFO read waveform so that i can get the SYNC frame out of the camera and get the video out of the camera. But i still don't understand completely the transition from the timing diagrams to the state diagrams using GPIF. The following points, I am having confusion with:
1. In my project, FSYNC will rise at least one clock cycle before LSYNC. I want to make sure that FSYNC and LSYNC are both 0 before i activate the data. But if the decision state I can't use if FYSNC = 0 and LSYNC = 0 because the second data value is always 1.
2. What should i use for the transaction counter? i am receiving 1 byte per pixel and it is 320 x 240 camera. Should i use the transaction counter to be 76800? I am confused that should I get frame in each FIFO read transaction. If yes, i want to use the AUTO IN mode, will the data be transferred automatically once the data buffer filled with 512 bytes?
I am attaching the timing diagram of the camera. Can you suggest any what would be the best way for me to get the video out of the camera.
I would really appreciate if someone can help me with this issue.
Implementing image sensor interface with Slave FIFO interface of FX2LP would be easier than going for GPIF.
Is there any specific reason for selecting GPIF for your application.
If you go for Slave FIFO interface, I think you just need to connect FSYNC to SLCS and LSYNC to SLWR. When both are valid the image sensor data will be written to the endpoint memory present in FX2LP. Endpoint will be decided based on FIFOADDR lines. You need to connect these FIFOADDR lines to ground If want to use EP2.
Let me know if you have any more questions on this implementation.
The only advantage of going for Slave FIFO is that the image sensor interface implementation will be easier. That's all. I thought you just started the project. If you had already developed the GPIF waveforms and all then go ahead with the same design. No need to change it now.
I will give my answers to your questions related to GPIF soon.
Thanks for your reply. We are still in developing phase And changing to slave fifi wouldn't be issue. If you can answer both in GPIF and slave FIFO would be really appreciated.
In slave FIFO you can choose to connect FSYNC to any GPIO pin and HSYNC to SLWR. That way, you can check the status of FSYNC inside firmware right?
Thanks for your reply. What about AutoIn Mode? We are not trying to use CPU just for perfomance purposes. Is this possible in AutonIn Mode?
AUTO mode always gives maximum performance compared to Manual mode as CPU does not come in the data path. Is your application using UVC class? If so, how are the headers being inserted. If there is no data modification required, then you can always choose AUTO mode.