Data Not Synced In the Beginning CY7c68013a

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Airian_007
Level 2
Level 2
5 replies posted 5 questions asked First solution authored

Hi,

i am facing an issue from couple of days and cannot figure out the solution. i am acquiring 16-bit ADC data from FPGA and streaming into PC using slave fifo interface of cy7c68013 and i have configured it as bulk 512. the issue is, i am getting few packets out of sync in the beginning of every transactions. i have attached screenshots of the acquired data. it vary in size but in most of the cases its about 6 packets of 512 bytes each. or less or sometimes 3072 bytes. its random but once i start acquiring it stays fixed unless i change the required number of samples or i change the length of the packets.

please suggest as how to rectify this issue. thanks  

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5 Replies
MallikaK_22
Moderator
Moderator
Moderator
50 likes received 750 replies posted 250 solutions authored

Hi,

Have you configured the endpoints properly in the descriptor file as well as TD_Init()?

Would it be possible to provide the wireshark traces for both the working and non-working cases? Also, can you provide your source code if not confidential for us to check?

Regards,

Mallika

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Hi,
thanks for your time,
i have attached images with comments for analysis. also i have attached the TD_Init(); routine. i tried to explain the issue with comments however, if any other information is required do let me know. i also want to know if its ok to add fail recovery mechanism in the code such as i case of bulkIN transfer failure i abort the current transfer and reset the pipe and it starts working again. if i don't do this the endpoint remain stalled. the error rate is not so high it appears very rarely.

Code:

void TD_Init( void )
{
CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
SYNCDELAY;

REVCTL = 0x03;
SYNCDELAY;

IFCONFIG = 0xE3; //Internal clock, 48 MHz, Slave FIFO interface
SYNCDELAY;

OEC = 0x03;
SYNCDELAY;
IOC = 0xFF;
SYNCDELAY;
OEA = 0x02; //PA0 --> (FPGA-->USB) /// PA1 --> (USB-->FPGA)
SYNCDELAY;
IOA = 0x00;
SYNCDELAY;

PINFLAGSAB = 0x08; // FLAGA - EP2EF
SYNCDELAY;
PINFLAGSCD = 0xE0; // FLAGD - EP6FF
SYNCDELAY;
EP2CFG = 0xA0; //out 512 bytes, 4x, bulk
SYNCDELAY;
EP6CFG = 0xE0; // in 512 bytes, 4x, bulk
SYNCDELAY;
EP4CFG &= 0x7F; //clear valid bit
SYNCDELAY;
EP8CFG &= 0x7F; //clear valid bit
SYNCDELAY;

SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL


// handle the case where we were already in AUTO mode...
// ...for example: back to back firmware downloads...
SYNCDELAY; //
EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=1
// core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's
SYNCDELAY; //
EP2FIFOCFG = 0x11; // AUTOOUT=1, WORDWIDE=1
SYNCDELAY; //
EP6FIFOCFG = 0x0D; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1
SYNCDELAY;

// INIT_CY22150();

}

void TD_Poll( void )
{ // Called repeatedly while the device is idle


if(PA_0 == 1 && done_frm_fpga == 1)
{
IFCONFIG = 0x13; //external clock input, Slave FIFO interface
SYNCDELAY;

IOC|=0x01; //output 1 on PC.0...SYNC signal is HIGH
SYNCDELAY;

done_frm_usb = 1;
done_frm_fpga = 0;
PA_1 = 1;
IOC = 0x02;
SYNCDELAY;
}
}

BOOL TD_Suspend( void )
{ // Called before the device goes into suspend mode
return( TRUE );
}

BOOL TD_Resume( void )
{ // Called after the device resumes
return( TRUE );
}

//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor( void )
{
return( TRUE );
}

BOOL DR_SetConfiguration( void )
{ // Called when a Set Configuration command is received

if( EZUSB_HIGHSPEED( ) )
{ // ...FX2 in high speed mode
EP6AUTOINLENH = 0x02;
SYNCDELAY;
EP8AUTOINLENH = 0x02; // set core AUTO commit len = 512 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x00;
SYNCDELAY;
EP8AUTOINLENL = 0x00;
}
else
{ // ...FX2 in full speed mode
EP6AUTOINLENH = 0x00;
SYNCDELAY;
EP8AUTOINLENH = 0x00; // set core AUTO commit len = 64 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x40;
SYNCDELAY;
EP8AUTOINLENL = 0x40;
}

Configuration = SETUPDAT[ 2 ];
return( TRUE ); // Handled by user code
}

 

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Airian_007
Level 2
Level 2
5 replies posted 5 questions asked First solution authored

I just figured out that the samples which are always out of sync are 128 (128 x 2 x8 = 2048) and using quad buffering for 512 bytes its 2048. It has to do something with the old data which is always there in the fifo. My scheme works like whenever the empty fifo flag from usb fifo goes high the fpga fills the fifo while observing fifo full flag no matter if the host requested data or not. That quad buffer will always be filled with some data and what i am seeing as out of sync is just an offset of 2048 bytes of old data. Now there has to be some mechanism which should flush the old data before acquiring continuous new data points.

Maybe its helpful to diagnose the issue.

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MallikaK_22
Moderator
Moderator
Moderator
50 likes received 750 replies posted 250 solutions authored

Hi,

Okay, in this case you may abort packets in the FIFO. Resetting the FIFO, after taking it out of the AUTOIN mode, empties the FIFO and sets the EMPTY bit.  Any packets in the buffers are skipped or invalid. Thus the sequence is:

1. Set the NAKALL bit

2. Switch to manual mode

3. Reset the FIFOs

4. Switch to auto mode

5. Release the NAKALL bit

For example,

TD_Poll ( ) :

… … …

if (FIFO_RESET)

{ //This is an example code segment which resets the EP6 FIFO

//where EP6 has been configured as AUTOIN

//Note: Settings of other bits of EPxFIFOCFG are ignored here FIFORESET = 0x80;

// activate NAK-ALL to avoid race conditions SYNCDELAY; EP6FIFOCFG = 0x00;

//switching to manual mode SYNCDELAY; FIFORESET = 0x06;

// Reset FIFO 6 SYNCDELAY; EP6FIFOCFG = 0x0C;

//switching to auto mode SYNCDELAY; FIFORESET = 0x00;

//Release NAKALL SYNCDELAY;

}

… … …

Kindly try this and let me know if this helps.

Regards,

Mallika

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hi,
i tried your suggestion and its working however, the issue is, i have to reset EP6 before every IN transaction. lets say if i want 10 packets of 512 bytes in a loop then i have to flush the endpoint at the start of 1st packet and  it works ok. below is the case where its working. 

while(1)

{

Reset_FIFO();

for(i = 0; i<=9;i++)

{

Fetch_Data();

}

below is the case which i want to implement but its not working

Reset_FIFO();

while(1)

{

for(i = 0; i<=9;i++)

{

Fetch_Data();

}

and please make comment on the failure recovery scheme as i mentioned in my previous post, if its the way to do it or do i have to dig into the issue to completely eliminate the failures.

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