Cy68013A Slave fifo Bulk read dummy(invalid) data

kjwang · ‎May 25, 2023

we use the EP6 transfer data from FPGA to PC ( IN )
set EP6CFG = 0xE0; // IN, 512-bytes, 4x, bulk
After the data update in FPGA device，read the data package，There are 4 * 512 bytes in front and are not valid data；

set the 2x, bulk
After the data update in FPGA device，read the data package，There are 2 * 512 bytes in front and are not valid data；

What is the cause of this problem ？

MallikaK_22 · ‎May 25, 2023

Hi,

Apologies but I'm a bit unclear on your question. What does it mean by data update in FPGA device?

Are you only doing IN transfers? Since there are 2 parts in the data path between FPGA and PC: (1) FPGA to FX2LP and (2) FX2LP to Host PC.

In which part are you facing the issue, i.e. if the data is being transferred from FPGA to FX2LP properly but not from FX2LP or PC or is the data between FPGA and FX2LP link is itself improper.

Regards,

Mallika

kjwang · ‎May 28, 2023

Hi ,

the 68013 firmware can be listed as follow

@kjwang wrote:

we use the EP6 transfer data from FPGA to PC ( IN )
set EP6CFG = 0xE0; // IN, 512-bytes, 4x, bulk
After the data update in FPGA device，read the data package，There are 4 * 512 bytes in front and are not valid data；

set the 2x, bulk
After the data update in FPGA device，read the data package，There are 2 * 512 bytes in front and are not valid data；

What is the cause of this problem ？

void TD_Init(void) // Called once at startup

{

// set the CPU clock to 48MHz

CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;

// Set Slave FIFO mode

IFCONFIG = 0xE3;

REVCTL = 0x01; // REVCTL.0 and REVCTL.1 to set to 1

SYNCDELAY;

PINFLAGSAB = 0xe8;//0xA8; // FLAGB - fixed EP2FF FLAGA - EP2EF

SYNCDELAY;

//PINFLAGSCD = 0xDE; // FLAGD - unvalid FLAGC - fixed EP6FF

SYNCDELAY;

PORTACFG = 0x01; // func. of PA7 pin is SLCS#

SYNCDELAY;

FIFOPINPOLAR = 0x00; // all signals active low

SYNCDELAY;

// we are just using the default values, yes this is not necessary...

SYNCDELAY; // see TRM section 15.14

EP2CFG = 0xA0; //EP2 OUT, 512BYTE BULK, 4 BUFFER

SYNCDELAY;

EP4CFG = 0x02; //EP4 OUT, BULK

SYNCDELAY;

EP6CFG = 0xE0; //EP6 IN, 512BYTE BULK, 4* BUFFER

SYNCDELAY;

EP8CFG = 0x02; //EP8 IN, BULK

// since the defaults are double buffered we must write dummy byte counts twice

SYNCDELAY;

EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.

SYNCDELAY;

EP2BCL = 0x80;

SYNCDELAY;

EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.

//RESET FIFO endpoint

SYNCDELAY;

FIFORESET = 0x80; // reset all FIFOs

SYNCDELAY;

FIFORESET = 0x02;

SYNCDELAY;

FIFORESET = 0x04;

SYNCDELAY;

FIFORESET = 0x06;

SYNCDELAY;

FIFORESET = 0x08;

SYNCDELAY;

FIFORESET = 0x00;

// handle the case where we were already in AUTO mode...

SYNCDELAY;

EP2FIFOCFG = 0x00; // AUTOOUT=0, WORDWIDE=0

SYNCDELAY;

EP2FIFOCFG = 0x31; // AUTOOUT=1, WORDWIDE=1

SYNCDELAY;

EP6FIFOCFG = 0x09; // AUTOIN=1, WORDWIDE=1

SYNCDELAY;

// out endpoints do not come up armed

// enable dual autopointer feature

//AUTOPTRSETUP |= 0x01;

SYNCDELAY;

OEA = 0x0A;

IOA = 0x0;

PORTACFG = 0x01;

}

I have two questions

the first , when i write the data from PC to FPGA by EP2, the first Word is ok , the second word is wrong , why ? the second word is lost !

kjwang · ‎May 28, 2023

The second question is , when we bulk in the data , the fisrt package . the second package the third package , the fourth package is invlid , the 5th package is ok

BULK IN transfer
0000 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0010 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0020 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0030 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0040 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0050 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0060 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0070 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0080 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0090 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00A0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00B0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00C0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00D0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00E0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00F0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0100 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0110 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0120 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0130 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0140 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0150 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0160 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0170 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0180 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0190 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01A0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01B0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01C0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01D0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01E0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01F0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
BULK IN transfer completed

BULK IN transfer, this pakage is ok
0000 F9 FA F9 FA F9 FA F9 FA F9 FA 0B 0A 0C 06 07 08
0010 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18
0020 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28
0030 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38
0040 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48
0050 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58
0060 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68
0070 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78
0080 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88
0090 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98
00A0 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8
00B0 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8
00C0 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8
00D0 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8
00E0 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8
00F0 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8
0100 F9 FA FB FC FD FE FF FF B4 70 06 52 6D 45 28 CA
0110 8C 4F E5 5D 54 9D 32 53 2D 75 CD 6F 15 94 8D 09
0120 2A EB 61 84 51 88 AE 54 34 A9 F1 22 4E BE 98 0D
0130 9C 3F 5A 05 95 16 AB 91 EB 45 CF 22 1B CC 4F 14
0140 F9 3B 2E D7 3E 17 FD 74 8F 5A 0D 03 EE 71 B3 F1
0150 04 42 7A 91 C2 40 67 13 33 E3 A8 A2 04 2F 06 CB
0160 4D 7C 7E 0F B6 00 B7 75 B4 C9 02 40 17 C8 04 D5
0170 11 30 13 C0 25 63 75 32 52 F5 28 B7 3C CF C8 BE
0180 BE 16 4D 75 8B 6C 39 5B 16 6B 0D FF 30 44 1B F3
0190 A8 E0 E9 07 75 6C 7C E8 E7 A1 DD AA 59 39 2B 01
01A0 7D 7B 47 C4 C1 4C 7B 66 60 82 C4 63 A4 4E 69 1F
01B0 B7 85 62 80 12 98 A2 57 3A 5D 09 2D 1E B1 B9 00
01C0 AA F3 A9 06 0C 6C 24 55 47 F8 44 67 44 C7 B5 C1
01D0 3C 6D 27 04 8F 66 2D C9 4F 86 4F E0 15 7A 1E B6
01E0 8C F2 AD 46 77 A9 9F 18 BD DA AD B5 18 62 0D CA
01F0 2F 57 14 D1 29 C7 F8 60 CD 26 E1 7E 27 AE 9D 9B
BULK IN transfer completed

kjwang · ‎May 28, 2023

the second question is , when bulk in the data from FPGA to PC used by EP6, the 1st 2nd 3 rd 4th package is invalid , the 5th is correct , why ?

BULK IN transfer
0000 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0010 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0020 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0030 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0040 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0050 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0060 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0070 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0080 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0090 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00A0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00B0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00C0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00D0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00E0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
00F0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0100 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0110 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0120 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0130 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0140 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0150 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0160 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0170 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0180 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
0190 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01A0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01B0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01C0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01D0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01E0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
01F0 01 82 01 82 01 82 01 82 01 82 01 82 01 82 01 82
BULK IN transfer completed

BULK IN transfer is right
0000 F9 FA F9 FA F9 FA F9 FA F9 FA 0B 0A 0C 06 07 08
0010 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18
0020 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28
0030 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38
0040 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48
0050 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58
0060 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68
0070 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78
0080 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88
0090 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98
00A0 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8
00B0 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8
00C0 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8
00D0 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8
00E0 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8
00F0 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8
0100 F9 FA FB FC FD FE FF FF B4 70 06 52 6D 45 28 CA
0110 8C 4F E5 5D 54 9D 32 53 2D 75 CD 6F 15 94 8D 09
0120 2A EB 61 84 51 88 AE 54 34 A9 F1 22 4E BE 98 0D
0130 9C 3F 5A 05 95 16 AB 91 EB 45 CF 22 1B CC 4F 14
0140 F9 3B 2E D7 3E 17 FD 74 8F 5A 0D 03 EE 71 B3 F1
0150 04 42 7A 91 C2 40 67 13 33 E3 A8 A2 04 2F 06 CB
0160 4D 7C 7E 0F B6 00 B7 75 B4 C9 02 40 17 C8 04 D5
0170 11 30 13 C0 25 63 75 32 52 F5 28 B7 3C CF C8 BE
0180 BE 16 4D 75 8B 6C 39 5B 16 6B 0D FF 30 44 1B F3
0190 A8 E0 E9 07 75 6C 7C E8 E7 A1 DD AA 59 39 2B 01
01A0 7D 7B 47 C4 C1 4C 7B 66 60 82 C4 63 A4 4E 69 1F
01B0 B7 85 62 80 12 98 A2 57 3A 5D 09 2D 1E B1 B9 00
01C0 AA F3 A9 06 0C 6C 24 55 47 F8 44 67 44 C7 B5 C1
01D0 3C 6D 27 04 8F 66 2D C9 4F 86 4F E0 15 7A 1E B6
01E0 8C F2 AD 46 77 A9 9F 18 BD DA AD B5 18 62 0D CA
01F0 2F 57 14 D1 29 C7 F8 60 CD 26 E1 7E 27 AE 9D 9B
BULK IN transfer completed

Cy68013A Slave fifo Bulk read dummy(invalid) data

Re: Cy68013A Slave fifo Bulk read dummy(invalid) data

Re: Cy68013A Slave fifo Bulk read dummy(invalid) data

Re: Cy68013A Slave fifo Bulk read dummy(invalid) data

Re: Cy68013A Slave fifo Bulk read dummy(invalid) data