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USB low-full-high speed peripherals Forum Discussions

Anonymous
Not applicable

Hi all

   

I am using CY7C68013A with EP2 set up as iso OUT endpoint. The data from FIFO buffers is read by external synchronous master (CPLD). The problem is that at random times FLAGA output configured as actile low EP2 empty flag becomes zero, and stays acitve, while host continues sending data to EP2, until I reset the CY7C68013A and reload the firmware.

   

 

   

What can be the reason of such behavior?

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8 Replies
Anonymous
Not applicable

Also, EP2 interrupt stops to trigger as well

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Anonymous
Not applicable

Here is the waveforms the FPGA generates

   

Each read cycle is 2 words per RD active. Host always sends packets which are multiple of 4 bytes.

   

FLAGA is sampled on falling edges of IOCLK, and if FLAGA is not active (FIFO not empty,  then SLOE is activated, then RD is activated on next  IOCLK falling edge. IOCLK freq is 6.25 MHz

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Anonymous
Not applicable

 Hi,

   

 

   

Please share things like in what mode (Auto/Manual) FX2LP is operating? Can you please paste your code here. I would like to take a look.

   

 

   

Regards,

   

Gayathri

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Anonymous
Not applicable

This is the initialization code:

   

    REVCTL = 0x00;
    SYNCDELAY();
    IFCONFIG = 0x03; // ext. clock, slave FIFO
    SYNCDELAY();
    EP1OUTCFG &= ~0x7F;
    SYNCDELAY();
    EP1INCFG &= ~0x7F;
    SYNCDELAY();
    EP4CFG &= ~0x7F;
    SYNCDELAY();
    EP6CFG &= ~0x7F;
    SYNCDELAY();
    EP8CFG &= ~0x7F;
    SYNCDELAY();
    EP4FIFOCFG = 0;
    SYNCDELAY();
    EP6FIFOCFG = 0;
    SYNCDELAY();
    EP8FIFOCFG = 0;
    SYNCDELAY();
    EP2FIFOCFG = 0x11; // Auto, wordwide
    SYNCDELAY();
    PINFLAGSAB = 0x08;

    //       Valid      Out        ISO        1024       QuadBuf
    EP2CFG = (1 << 7) | (0 << 6) | (1 << 4) | (1 << 3) | (0 << 0);
    SYNCDELAY();
    FIFORESET = 0x80;
    SYNCDELAY();
    FIFORESET = 0x82;
    SYNCDELAY();
    FIFORESET = 0x00;
    SYNCDELAY();
    EP2BCL = 0x80;
    SYNCDELAY();
    EP2BCL = 0x80;
    SYNCDELAY();
    EP2BCL = 0x80;
    SYNCDELAY();
    EP2BCL = 0x80;

    //debug pin
    OEA = 0x03;

 

   

And this code is executed when host selects interface:

   

        FIFORESET = 0x80;
        SYNCDELAY();
        FIFORESET = 0x82;
        SYNCDELAY();
        FIFORESET = 0x00;
        SYNCDELAY();

        TOGCTL = 0x02;
        SYNCDELAY();
        TOGCTL = 0x22;

        EP2BCL = 0x80;
        SYNCDELAY();
        EP2BCL = 0x80;
        SYNCDELAY();
        EP2BCL = 0x80;
        SYNCDELAY();
        EP2BCL = 0x80;

 

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Anonymous
Not applicable

Hi, 

   

 

   

Please try replacing

   

    FIFORESET = 0x80;
    SYNCDELAY();
    FIFORESET = 0x82;
    SYNCDELAY();
    FIFORESET = 0x00;
    SYNCDELAY();

   

with

   

    FIFORESET = 0x80;
    SYNCDELAY();
    FIFORESET = 0x02;
    SYNCDELAY();
    FIFORESET = 0x00;
    SYNCDELAY();

   

 

   

Regards,

   

Gayathri

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Anonymous
Not applicable

If I do so, FLAGA is always active (FIFO empty)

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Anonymous
Not applicable

I have noticed that when this problem occurs, ISOEP2 bit in USBERRIRQ is set

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Anonymous
Not applicable

 Hi,

   

 

   

Please cerate a tech support case at www.cypress.com, so that and one of engineers can take a look at it and help yo out.

   

 

   

regards,

   

Gayathri

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