CY7C68013A Slave FIFO hangs after External Clock Failure - How to Recover?

[FrZa_2625781]

Hi,

I use the CY7C68013A in Slave FIFO mode with external clock.

When the externally supplied IFCLK fails due to some reason, the FIFO becomes stuck, even if the external clock is revived.

Currently, the only remedy I know of is pulling the USB plug.

I know that the external IFCLK must be present before switching to external clock, but bad things happen sometimes.

What can I do if the external clock starts too late or has been off or below the minimum frequency temporarily (other than pulling and re-seating the USB plug)?

Thanks!

P.S.:

Disabling and re-enabling the device or the USB root hub in the Windows Device Manager (-> new enumeration) does not solve the problem.

[MallikaK_22]

Hi,

You can initially configure IFCONFIG register to use internal IFCLK and then IFCONFIG.7 is modified to take IFCLK from the external source once it is ready.

Regards,

Mallika

[FrZa_2625781]

That is exactly what I do.

But when the external source has a drop-out afterwards, it hangs, even if the external clock comes back on.

Only "solution" known to me at the moment is pulling the USB plug, which I cannot do remotely.

I just tried to switch back to internal source (write 83 into IFCONFIG) and then external again (IFCONFIG back to 03), but that doesn't help either.

In fact, if I do that while everything is OK, the interface hangs itself up just like if the external clock had dropped out.

Can the internal clock be disabled somewhere else?

[MallikaK_22]

Hi,

Apologies but there is no recovery mechanism available for such a situation. This is not an ideal operating condition as well. When you have configured the clock source to be external, it is expected that the clock source should be stable. Otherwise, without proper clock, FX2LP won't work.

Once you set IFCONFIG.7 to 0 (i.e. external), the FX2LP firmware waits for external clock to stabilise before executing the state machine. Please ensure that the external clock is stable at all times otherwise use the internal clock.

Regards,

Mallika

[FrZa_2625781]

Hi,

would a hard reset help?

IIRC I have a GPIO pin left that is unused.

If a hard reset would recover the chip, I could connect it to Reset and set it to 0 for resetting the chip without having to pull the USB plug.

Or is loss of supply voltage (pulling the plug) the only way of recovery?

[MallikaK_22]

Hi,

Yes, reset should work. But again please ensure the proper clock source is present and stable before changing the register setting in the firmware.

Regards,

Mallika

[FrZa_2625781]

Thanks!

I make sure that it is stable before I change the register to external clock, but as we live in a non-ideal world, things happen.

I'll thy to tinker in a connection from the unused GPIO pin to the reset pin. After setting the GPIO pin low, the chip should enter reset, thereby making the GPIO pin high impedance, activating itself again.

What is also intereting:

The chip doesn't always get stuck when the IFCLK dies and is revived again. Could it be possible, that the slave FIFO "survives" a missing IFCLK if the according endpoint is stalled due to the buffers being full?

I just stream the data into the endpoint regardless of any flags because even if I would stop with a full buffer, further data would get lost anyways.

So if I don't actually need the data, I just stop sending input transfer commands to the driver and let the buffers run full. If I want to collect the data again, I just initiate new transfer commands (and discard the first 2kB as that would be old data from when I stopped polling the chip).

Now, if I stop polling the data and let the buffers run full and stalled, it seems I can switch of the external oscillator without any problem, as long as I switch it back on before I empty the buffers and un-stall the endpoint.

Does this make sense to you?