I have a CY7C68013A-based design that I am supporting.
The design uses the GPIF to interface with an FPGA. We are using the IFCLK in internal mode (48MHz), undriven. The FPGA is clocked by CLKOUT (also 48MHz). I am trying to understand whether there is a known timing relationship between these 2 clocks, or whether I need to treat the GPIF as asynchronous to CLKOUT. I have not found any reference to a relationship between these 2 clocks in any of the documentation that I have.
Solved! Go to Solution.
IFCLK is used when interfacing FX2LP with an external peripheral using Slave FIFO or GPIF and be used as input or output from FX2LP.
IFCLK is necessary for synchronizing the transfers between external peripheral and FX2LP (configured as GPIF or Slave FIFO).
CLKOUT is used to clock an external peripheral continuously if required. For example, on startup, if an FPGA is connected to FX2LP and the FPGA needs an external clock to configure itself on startup, CLKOUT from FX2LP can be used.
For data transfers in Slave FIFO or GPIF mode IFCLK should be used.
Thank you for your response!
In our design (which I inherited), the IFCLK is set to internal mode, but is not driven out by the EZ-USB, so I don't have access to it. Since both IFCLK and CLKOUT are generated by the CY7C68013, I was hoping that there was a known relationship between the 2 clocks that I could use to perform a timing analysis on our use of the GPIF interface. In this context, are the IFCLK and CLKOUT really asynchronous?