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USB low-full-high speed peripherals Forum Discussions

abhishekps
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

Hi,

I am using FX2LP kit with FPGA along with UVC implementation for displaying a video over VLC.
When I try to fetch data from FX2LP as a USB controller on USB control center, I am able to get fetch correct data from buffer.

But when I am using UVC framework with the same setting of worldwide = 0. I am getting less and wrong data in first data fetch. I have checked this using wireshark. Also attaching a screenshot to elaborate my issue.

abhishekps_0-1627554382855.png

In this image my first packet data length should be of 16380 bytes instead of 16028 bytes and starting of data is also wrong.

Is there some additional setting that I should do in case of UVC implementation?

 

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1 Solution
MallikaK_22
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 250 replies posted

Hi,

>> Is 48 Mhz used in the PASS case also provided from FPGA ?

>> Can you please share the oscilloscope/analyzer traces for both the PASS & FAIL case.

>> Please also refer to this KBA to ensure the mentioned design aspects are being considered: https://community.cypress.com/t5/Knowledge-Base-Articles/IFCLK-internal-external-Design-aspects-to-c...

>> Please make sure that all the timing constraints are met. Refer to FX2LP data sheet "Slave FIFO Synchronous Write Timing Diagram" and Table 24 for the timing constraints.

Regards,

Mallika

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9 Replies
abhishekps
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

Hi,

I was able to resolve this wrong data issue. Now I am able to receive correct data on UVC FX2LP device, but still not able to display any video over it.
With the same data I was able to see video on VLC when I was using 16-bit synchronous transmission. Don't know why I am facing issue with 8-bit synchronous setting.

 

Earlier also when I tried with different variable frequency like 20Mhz on IFCLK I was getting the same issue. 

Please suggest what could be wrong.

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abhishekps
Level 3
Level 3
25 replies posted 25 sign-ins 10 replies posted

Hi,

Gentle reminder. Please help here.

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MallikaK_22
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 250 replies posted

Hi,

I'm sorry I could not understand properly. Are you getting video data from FPGA with 8 bit synchronous setting ? 

Regards,

Mallika

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Yes, I am getting video data from FPGA with 8-bit synchronous setting. I was facing issue in getting video display on VLC. But I noticed that header byte sequence was wrong from FPGA end and that has been resolved few minutes ago.

But I am facing a new type of issue in FX2LP device. I am trying to provide 20 Mhz IFCLK instead of 48 Mhz from FPGA but I am not able to get any data over UVC. I also checked with USB control center(FX2LP as a USB controller device) it works with 48Mhz but fails to get any data in case of 20Mhz.

I also tried with 13 Mhz and I am getting some data but it is not the exact data that I am expecting.

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MallikaK_22
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 250 replies posted

Hi,

>> Is 48 Mhz used in the PASS case also provided from FPGA ?

>> Can you please share the oscilloscope/analyzer traces for both the PASS & FAIL case.

>> Please also refer to this KBA to ensure the mentioned design aspects are being considered: https://community.cypress.com/t5/Knowledge-Base-Articles/IFCLK-internal-external-Design-aspects-to-c...

>> Please make sure that all the timing constraints are met. Refer to FX2LP data sheet "Slave FIFO Synchronous Write Timing Diagram" and Table 24 for the timing constraints.

Regards,

Mallika

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Hi Mallika,

>> 48Mhz is also provided by FPGA.

>> Currently I am not able to arrange for DSO, as soon as I get it I will share you the waveform.

>> I checked the referred KBA mentioned by you. The settings mentioned in that was missing in my project. I added that but issue remains same.

>> I will check these timing specs as soon as I get the DSO.

>> Apart from these points if I have to move from 48Mhz Ext CLK to 20Mhz Ext CLK what are the settings I need to change in FX2LP?

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Adding to above points, actually I checked previously with DSO and found that my SLWR pin is not showing any activity even though FLAGB is showing empty status(LOW STATE).

According to FPGA simulation, when FLAGB is in LOW STATE SLWR pin should also go low.

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MallikaK_22
Moderator
Moderator
Moderator
250 solutions authored 500 replies posted 250 replies posted

Hi,

The design aspects & timing constrains should be met when using IFCLK at any frequency.

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Hi Mallika,

I observed that behavior on 20 MHz of our setup was totally different than behavior of 13 MHz and 25Mhz.
So we checked and found that Microsemi FPGA is not working properly on 20 MHz with the same code which works fine on 48MHz. So for now we will be focusing on Understanding what setting is required in FPGA. Maybe due to incorrect setting of FPGA device is misbehaving.

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