CY3689 DK || Implementing hardcoded video streaming || UVC example

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abhishekps
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25 replies posted 25 sign-ins 10 replies posted

Hi,

Can we implement hardcoded values for video streaming via UVC?

I have a use-case where we are to develop a PC app for video streaming via FX2LP(CY3689 DK). Can I get(or develop) an example code where we are sending hardcoded data as video data to display over any media player(like VLC player)?

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Pranava_YN
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100 likes received 500 replies posted 250 solutions authored

Hi,

It is possible for FX2LP to send hardcoded USB data to the host. You can refer to CYstreamer example project for this.

However while implementing UVC class, FX2LP is not fast enough to insert header and footer between each frame while streaming. So, an FPGA is required to append header and footer to the video data and pass it to FX2LP. 

Best regards,
Pranava

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Pranava_YN
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100 likes received 500 replies posted 250 solutions authored

Hi,

It is possible for FX2LP to send hardcoded USB data to the host. You can refer to CYstreamer example project for this.

However while implementing UVC class, FX2LP is not fast enough to insert header and footer between each frame while streaming. So, an FPGA is required to append header and footer to the video data and pass it to FX2LP. 

Best regards,
Pranava
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Hi Pranava,

Actually I didn't find CYstreamer example for CY3689 DK, it is available for CY3684 but I am not able to either run or modify the code for CY3689 DK.

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What if I hardcoded the frames headers along with hardcoded data? It won't be a problem then right?

Also how if slave fifo buffer(input from FPGA) linked to UVC output buffer?

I have FPGA + UVC example, but doesn't have FPGA to test it right now. Can I just make small change in the existing example code to display hardcoded data along with UVC headers?

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Pranava_YN
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100 likes received 500 replies posted 250 solutions authored

Hi,

You can find all the details about streamer and the source codes in the App note - https://www.cypress.com/documentation/application-notes/an4053-streaming-data-through-isochronous-or...

This example is built for CY3684 kit, therefore you will not be able to run it directly. Please note that you will also not be able to build the project as free version of Keil provided has code limit of 4kb. I am attaching the modified streamer firmware which is suitable for CY3689 kit. Please use the same. You can always refer to project source from the app note.

If all data including frame headers are hardcoded, then it will not be an issue for FX2LP.

Also how if slave fifo buffer(input from FPGA) linked to UVC output buffer?

>>FX2LP has 2 data domains, USB domain and Interface domain. Slave FIFOs section of FX2LP TRM (https://www.cypress.com/documentation/technical-reference-manuals/ez-usbr-technical-reference-manual) provides an elaborate explanation of data transfers between these domains and different modes that can be used.

Do let me know if you need any further clarification regarding this.

Best regards,
Pranava
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