About External clock of FX2LP

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Ray0124
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First solution authored 10 sign-ins First reply posted

Hi all , I use  AN61345 example(FPGA with slave FX2LP). I change the clock of FX2LP from FPGA(external) successfully ,but i have problem that it seems the fifo flag is useless when I change the clock from external. I use flaga for EP2 . It work normally under internal clock. But when I change external clock , and I put data to ep2, the flaga is always empty. Does anyone have idea?

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MallikaK_22
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50 likes received 750 replies posted 250 solutions authored

Hi,

When using clock from an external source, please note "in order to provide synchronization for the internal
endpoint FIFO logic, the external IFCLK source must be present before the firmware is running and it sets IFCONFIG.7 = 0".

Kindly ensure that the following requirement is being met.

Regards,

Mallika

 

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MallikaK_22
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50 likes received 750 replies posted 250 solutions authored

Hi,

When using clock from an external source, please note "in order to provide synchronization for the internal
endpoint FIFO logic, the external IFCLK source must be present before the firmware is running and it sets IFCONFIG.7 = 0".

Kindly ensure that the following requirement is being met.

Regards,

Mallika

 

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Hi , thx for reply. Yes ,I send ifclk before the firmware burn in. I use OSC of fpga to use PLL to generate 48MHz for state machine on fpga, and shift 180 degree 48Mhz for ifclk. I didn't use the clockout of fx2. Does it will matter?  

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Hi , I also check I send ifclk before I set ifconfig.7=0(change external), but the flag seems not to work.

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MallikaK_22
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50 likes received 750 replies posted 250 solutions authored

Hi,

In our example firmware, we initially configure IFCONFIG to use the internal IFCLK. This is because FX2LP firmware cannot configure the IFCONFIG register to work with external clock before configuring the FPGA to supply the interface clock (Note that the external IFCLK source must be present before the firmware sets IFCONFIG.7 = 0 and IFCLK is provided by external source here).

So to meet this condition, initially IFCONFIG register is configured to use internal IFCLK and then
IFCONFIG.7 is modified to take IFCLK from the FPGA once FPGA is up and running with the bit-stream.

Could you please share your firmware source if not confidential.

Regards,

Mallika

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Hi , thx for replying. I use AN61345 fpga code (just modify fpga PLL for altera) and fx2 firmware (I change the TD_pol , other parts are the same). I make sure the ifclk is sending before the FX2LP change external clk. 

void TD_Poll( void )
{ // Called repeatedly while the device is idle


if (test == 0)
{
SYNCDELAY;
IFCONFIG = 0x03; //external clock input, Slave FIFO interface
SYNCDELAY;
IOC|=0x01; //output 1 on PC.0...SYNC signal is HIGH
SYNCDELAY;
test = 1;

}
}

#################################################################

By the way, can I use FX2LP to produce ifclk to support FPGA? 

 

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MallikaK_22
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50 likes received 750 replies posted 250 solutions authored

Hi,

Apologies for the delay in my response.

Yes, it is possible to feed IFCLK from FX2LP to FPGA. IFCONFIG.6  should be set to internal clock enabled and IFCONFIG.5 , i.e. the output enable for internal clock source should also be set to 1.

Regards,

Mallika

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