hi, i have a problem about cy7c67300 work in coprocessor mode.

normally cy7c67300 work fine, but sometimes cy7c67300  look like dead. i use cy7c67300 in coprocessor mode, use HPI read its register, normally mailbox interrupt is order, but sometimes HPI Status Port register bit 8 is 1, it indicate Mailbox in flag, so , i think Cy7c67300 on-chip is dead, it can't read from the HPI Mailbox register , the interrupt can't clear , and  my application can't work.

i wan't to konw , on this occasion , what can i do ,. i want to reset it, but i don't konw  how to do it.

i hope to get your help ,thank you!

I have a question about CY7C67300 after going through the data sheet.

1. I would like to use CY7C67300 in co-processor mode with HPI port interface. I need two Host ports and One device ports. I was planning to use port 1A as peripheral and ports 2A and 2B as Hosts. In this configuration what does the OTGID pin have to be tied to +3.3V or GND or left floating as I intend to use that port as a peripheral. Also is this configuration valid to use meaning port 1A as peripheral and 2A and 2B as hosts.

2. Can I use GPIO pins to use as Enable input to a USB Power Switch to provide 500mA current and use the FLAG output from the USB power switch back into CY7C67300 to check for over current situations.

3. I came across some other application note from Cypress about HPI port and I am confused by one statement I found in it. It stated that BIOS will not configure port 1A or 2AS in co-processor mode. What does this imply? How else would I configure port 1A as peripheral and port 2A as host?

Thanks.

Hello I am workin on the project about the creation of Ip in vhdl to communicate avec FX3 in sync slavefifo mode.

are there any people that have already work in this part of subject to give me some advices about that or anything that can help me ?

my goal is to establish communication between FPGA(Ip) ====>FX3 (just one signle side). To do that  I must use timing from sync slave fifo but this timing seems not really easy to understand.

regards,

 Hello friends, I need to create a USB OTG interface to make APPLE Iphone or IPAD USB OTG compatible to allow me to transfer Photos and documents between my Android Samsung Note Edge and my Iphone/ IPAD, OR is there any way to connect an External Flash Drive to APPLE Iphone or IPAD to allow bi directional transfer of Photos and documents between the Flash drive and the Iphone or IPAD or at least just being able to transfer PHOTOS from and Iphone or IPAD to the flash drive and from Flash drive to the Iphone/IPAD. Any suggestions or ideas?

Any HW and or SW solution to accomplish that? Does Cypress or other mfg have any IC that can help me accomplish the above Flash drive solution. Or is this just a SW solution or combination to save Photos and or documents from Iphone to flash drive and back to Iphone. Thanks Avi 

Hi,

I have a board that I need to write some software to test the USB controller (SL811HST). Is there a free USB stack I can use with the SL811HST to access a memory stick?

Thanks

Adrian

I am trying to run se1 design with GDB
( see "USB Multi-Role Device Design By Example" chapter 3).
But I can't do it. I get GDB errors
"You can't do that when your target is `exec".
What can be the reason?

We have a new board design using the CY7C65642 hub chip connected to USB0 of the AM3356 CPU and a type B connector to USB1. I can see that linux detects the hub during boot-up, but nothing plugged into the hub's USB ports is detected.

This is my output:

[    0.171477] usbcore: registered new interface driver hub
[    0.171924] usbcore: registered new device driver usb
[    0.172568] registerd cppi-dma Intr @ IRQ 17
[    0.172601] Cppi41 Init Done Qmgr-base(d083a000) dma-base(d0838000)
[    0.172623] Cppi41 Init Done
[    0.172676] musb-ti81xx musb-ti81xx: musb0, board_mode=0x21, plat_mode=0x1
[    0.173274] musb-ti81xx musb-ti81xx: musb1, board_mode=0x21, plat_mode=0x2
[    0.177398] Advanced Linux Sound Architecture Driver Version 1.0.24.
[    0.179943] Switching to clocksource gp timer
[    0.219111] musb-hdrc: version 6.0, ?dma?, otg (peripheral+host)
[    0.219452] musb-hdrc musb-hdrc.0: dma type: dma-cppi41
[    0.220994] musb-hdrc musb-hdrc.0: MUSB HDRC host driver
[    0.221182] musb-hdrc musb-hdrc.0: new USB bus registered, assigned bus number 1
[    0.221403] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    0.221439] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    0.221472] usb usb1: Product: MUSB HDRC host driver
[    0.221497] usb usb1: Manufacturer: Linux 3.2.0-ts-armv7l musb-hcd
[    0.221524] usb usb1: SerialNumber: musb-hdrc.0
[    0.223284] hub 1-0:1.0: USB hub found
[    0.223351] hub 1-0:1.0: 1 port detected
[    0.224546] musb-hdrc musb-hdrc.0: USB Host mode controller at d081e000 using DMA, IRQ 18
[    0.224885] musb-hdrc musb-hdrc.1: dma type: dma-cppi41
[    0.227153] musb-hdrc musb-hdrc.1: USB Peripheral mode controller at d0832800 using DMA, IRQ 19

SET_PORT_NUM1 and SET_PORT_NUM2 are connected to GND so the hub should be using all 4 ports, but it doesn't seem to me like it's detecting the 4 ports of the USB hub.

Also, is the VID and PID detected related to this hub? From the documentation it looks like a different VID/PID: 0x04B4 and 0x6572.

Thanks in advance for any help or suggestions.

Dear Moderator:

If you would, please confirm that my assumptions below are correct regarding
CY67300 in coprocessor mode:

Are these assumptions correct for Coprocessor mode?
-------------------------------------------------------------------------------------
1. In coprocessor mode, the CY67300 only runs it's bios, no other SW is loaded.

2. The CY67300 comes with this bios already programmed in so there is no code for the user
to flash into the device.

3. All control to the device is done via the master interface of choice (in my case SPI)
using Link Control Protocol commands to directly manipulate the 67300 registers.

4. As a USB memstick controller, you are essentually accessing at the sector rd/wr level,
and I will have to construct these sector rd/wr command sequences as register commands.

5. Because of #4 the master must provide it's own FAT system.

6. No external memory is required for coprocessor mode, although extra RAM could be
   added and used by the master CPU through LCP commands.

7. In coprocessor mode, the device can be switched between master, otg, and slave modes
without resetting it.

8. I can put the CPU to sleep in Coprocessor mode.  A USB device detect would wake it up.
 

Additional Questions for coprocessor mode
----------------------------------------------------------------
1. Will thee CY67300 will automatically detect a USB device and perform enumeration when programmed as a host?

2. Will a new device insertion generate a status change (for intrerrupt at the master) on a GPIO pin?

3. Would using one of your master apps be a better choice for memstick control?  Would I have to build a custom
communications interface to my master CPU in the CY67300?   I know this is open-ended question; I am trying to balance the
simplicity of the coprocessor function vs the extra work of having to have my own FAT, etc.

Thank you for your answers 🙂