USB hosts hubs transceivers Forum Discussions

Hi, we are using a HX2VL Hub on our product and would like to program our own VID/PID. Do you have any manufacturer driver for Win 7/8/10 to be used with Blaster software?

Thanks !

Franck.

Hi support,

I have a project using CY7C65631 as a HUB USB 4 ports. Currently, I am using PWR# pins to enable external USB power switch. I already checked on the CY7C65631 datasheet but I do not know the PWR# pin status when the HUB USB power off.

Could you please help us on this case?

Thanks,

Ty

We are planning on using a CYUSB332x Hub controller for a new product.  There will be a USB 3.0 Host tablet to connect to devices through this hub.  The tablet will be the Host, but we want the Hub to also charge the tablet.  Typically, a Host device would provide power to the devices, but in our case we want the host to receive power to charge it's own battery.

Can this be done?  If so, how?  What are the requirements?

Thanks for any advice.

Steve

Hello

Regarding the USB HUB specifications, I think that it is possible to stop VBUS supply of the downstream port individually . If correct, is it ok to think that I can use the following Host comand? And, is it okay to think that the follwoing command can stiop DS VBUS for both USB2.0(HX2VL) and USB3.0 HUB(USB3.0)?  Otherwise, please let us know, If there are some other method to stop VBUS supply of the DS individually

・ Clear Hub Feature (CLEAR_FEATURE)

Best Regards

Arai

We are utilizing the CY7C65630-56LTXI in a piece of test equipment. The solution is completely embedded, with the host-port connecting to a phy & SoC. Industry standard tools have been used during design to help ensure signal integrity, length matching, impedance control, and timing. There is no configuration of the Hub, as we use it in its default state. Pull-up/downs have been placed on the SPI lines per the application notes provided from Cypress's website.

We have port3 of the hub that attaches (via a USB2.0-qualified analog-switch) to an Atmel ATSAMA5D35 processor ( to its integrated Phy). The linux running on the Atmel only loads the "device-mode" drivers.

When we command this switch to "connect" the ATSAMA5D35 USB to the Hub, we get intermittent issues including

  a) Port3 USB status light blinked 3 times before establishing link

  b) Port3 USB status light blinked 3 times, but no link established, led goes dark

  c) Port3 USB status light blinked once, and got legitimate link immediately.

  d) Port3 USB status light came on momentarily, then crashed entire Hub and ALL link lights go dark  <- this is our most troublesome case that I am asking about

While I admit there may be a signal integrity issue that is causing a weak link between the USB Hub port3 & the Atmel ATSAMA5D35, what would cause the entire USB hub to lock up, requiring a power-cycle to clear the fault?

We need assistance with this issue - are there known modes that the Hub can enter that would cause it to completely lock up

thanks in advance

Dear Nada

回答ありがとうございます。

但し、まだ解決には至っていないので幾つか質問をさせて下さい。

PHYとは何を指していますか。CY7C64225のことですか。

VIOの規定にはVBUS , D+ , D- も含まれていると言うことですか。

私が考えている回路（添付ファイル参照）では、UART側の電源もVDDと一緒に他の3.3Vも OFFされれます。

読んでいるマニュアルはDocument Number: 001-76294 Rev. *Gです。

話の行き違いがないように、電話にてお話をしたいので下記までお電話を頂くか、Nada様の電話番号を

教えて下さい。

2018-07-19 16:11 GMT+09:00 Nada Dianah Binti Azmi <

community-manager@cypress.com>:

<http://www.cypress.com>

Cypress Developer Community

<https://community.cypress.com/?et=watches.email.thread>

Self Power Design of CY7C64225

reply from Nada Dianah Binti Azmi

<https://community.cypress.com/people/ndma?et=watches.email.thread> in *USB

Hosts, Hubs, Transceivers* - View the full discussion

<https://community.cypress.com/message/163281?et=watches.email.thread#163281>

------------------------------

Self power designを使い、外部電源に接続していない場合は、VBUSは3.3Vで、PHYに電力が供給されます。

VDD=0Vなので、理想的にはVIOは0Vになり、絶対最大定格を超えてはなりません。

>

よろしくお願いいたします。

Nada

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Hello.

I see that the sample schematic for CYUSB3304  has a circuit for over-voltage protection. So, when the VBUS gets above around 5.8V, then the VBUS_US pin gets disabled. Does the chip kill the power by the PWR_EN pin to the power switch chip (U5) after VBUS_US goes low?

Alin

Hello I use the cy7c67200 (EZ-OTG) on a fpga (Altera DE2-115). I successfully implemented The enumeration process with help of the document "Using HPI in Coprocessor mode with OTG-Host -AN6010"

and want to read now some data from a usb flash drive.

But i have issues on that. Im not fully sure if I understand right how to do that, sadly i didnt found any examples which don't use high level frameworks and

where i can see how i send CBWs (command block wrapper) and how i receive the CSW (Command Status Wrapper).

Thats why i like to describe how i do it in the hope someone can tell me if I do it right in general .

What i do is: i issue a bulk reset.

Then i write a setup TD (Transfer Descriptor) which points with its BaseAddr to the CBW content.

CBW (on position 0x50C):

DataTransferLength 0x200

CDB: 28 00 00 00 00 00 00 00 08 00

My wMaxPacketSize as reported by the endpoint descriptor is 64 so i think I have to define the length in the CDB as 8 if i want 512bytes?

TD (at position 0x500):

base_addr: 0x50c

port_length:  0x1c

pid_ep:       0x12

dev_addr:     0x2

ctrl_reg:     0x41

status:       0x0

retry_cnt:    0x1b

residue:      0x0

next_td_addr: 0x528

Then i write a (data) TD with PID_IN and point with the BaseAddr where i want the data should be written.

TD (at 0x528)

base_addr: 0x534

port_length:  0x200

pid_ep:       0x91

dev_addr:     0x2

ctrl_reg:     0x1

status:       0x0

retry_cnt:    0x1b

residue:      0x0

next_td_addr: 0x734

Then i write a (status) TD which points with BaseAddr where i want to read the CSW

base_addr: 0x740

port_length:  0x0

next_td_addr: 0x0

Then i set the CurrentTDPointer to 500 and wait until the HPI_STATUS register reports TDListDone.

Then i read the data buffer at 0x534 where I expect the content from my usb device and i read the content

from 0x740 where i expect my CSW content.

But the data contains garbage, the csw signature for example is wrong and the csw tag is not equal to the value in my cbw.

Also the data which should be the 512 bytes of the flashdrive from LBA: 0 are not identical with the contents from the flashdrive.

Hello Cypress.

Could you please let us know noise tolerance of CYUSB3314?

Below capture is noise tolerance of CYUSB3314 at DS(Table 8. DC Electrical Characteristics).

But DS does not describe noise ripple frequency.

Our customer would like to know noise tolerance of CYUSB3314 under below conditions(1 to 4).

Could you please let us know noise tolerance value under both 1.2V and 3.3V conditions.

1. Max p-p noise level permitted when noise ripple frequency is “0.1MHz”.
2. Max p-p noise level permitted when noise ripple frequency is “0.2MHz”.
3. Max p-p noise level permitted when noise ripple frequency is “0.3MHz”.
4. Max p-p noise level permitted when noise ripple frequency is “Above 1.0MHz”.

And does voltage noise tolerance level described in DS change by noise ripple frequency?

Best Regards.

Yutaka Matsubara

Hi,    

I'm Dinesh Katkar from Acclivistech , Pune . I have selected USB hub controller IC CY7C65631-56LTXC for one of my product design and I would like to request you to support us for below my query.    

1) This Hub IC need to program while installation of all machine and it is time consuming for us.

Could you please recommend me Pre- programmed USB Hub controller chip from Cypress..    

Looking forward for your positive response!!