Hello, I'm using a CYUSB3324-88LTXC hub on a xilinx zynqmp system and I'm having some trouble getting it into USB3 mode. I am using it in default ROM mode (no eeprom installed) with pin strapping off. Currently everything enumerates fine but in USB2 mode.

I'm trying to isolate whether it is a problem with the zynq or something with the hub. The hub always enumerates a PID of 6506 indicating it's in USB2 mode. Datasheet states that ROM mode should have USB3 enabled by default.

2: Hub, USB Revision 2.10
- Class: Hub
- PacketSize: 64 Configurations: 1
- Vendor: 0x04b4 Product 0x6506 Version 80.0
Configuration: 1
- Interfaces: 1 Self Powered Remote Wakeup 0mA
Interface: 0
- Alternate Setting 0, Endpoints: 1
- Class Hub
- Endpoint 1 In Interrupt MaxPacket 1 Interval 12ms
- Endpoint 1 In Interrupt MaxPacket 1 Interval 12ms

So, if the default is USB3 mode, then under what circumstances will it give the 6506 PID for USB2?

Hi, there is something strange in their development kit, they don't filter the analog and digital voltages correctly.
There is a mix-up there that I don't understand.
If you notice, in the attached picture, there are DVDD voltages connected via a ferrite bead, and some not.

The same about AVDD some are connected via a ferrite bead and some are directly connected to a power supply with VDD_IO which is digital.
Is that the right way to separate the analog and digital supplies?
I usually separate analog and digital supplies with a ferrite bead.
Thanks for the helpers!

I want to do USB2.0 compliance test Host CHIRP Timing for HX2LP.

Is it necessary to switch modes internally to perform this test? Or, can the test equipment automatically judge and test (does HX2LP not need to control anything)?

If any control is needed, could you tell me how to do it?

Please refer to the diagram as follows for the configuration of the test.

Thanks,
Tetsuo

 Hi 

I'm using CYUSB3304-68LTXC  and find sometimes the usb connection is disconnected (Connected from PC to one FPGA baord). Would you please help check the schematics? And it seems the communication get disturbed, so I'm looking for the reference layout design, but cannot find it so far...

Thanks!

Hello,

Please let me know about the wafer process, assembly and testing process for HX2VL.

MPN : CY7C65632-28LTXC

I found the post below but the link was unreachable.

https://community.infineon.com/t5/USB-hosts-hubs-transceivers/CY7C65632-28LTXC/td-p/54068

Best Regards,

Naoaki Morimoto

Hello Team, I am assuming that AMBER indicator pin is used for representing error conditions. I want clarification with respect to error conditions - is it only power related error conditions- Over current or is it data related? Is there a list of error conditions which is being represented by AMBER indicator pin?

Thanks in advance!

The data sheet of HX2VL has the following description.

The internal reset is initiated, when there is an unstable power event for silicon’s internal core power (3.3 V ± 10%). Internal reset is released 2.7 µs ± 1.2% after supply reaches power good voltage (2.5V to 2.8V).

After starting up to the normal voltage (3.3V), how many volts does the voltage droop before the POR sequence starts again? Doesn't POR start until it droops to 2.5V?

HX2LP has no description in the datasheet, but is it the same rule?

Thanks,
Tetsuo