USB superspeed peripherals Forum Discussions

Hello,

In my application, fx3 has 4 endpoints, 0x1,0x81,0x2,0x82.
Those 0x1,0x81 are designed to transfer data while 0x2,0x82 are for video.
The DMA for video is set as AUTO mode for maximum throughput(Full HD video), while the data channel is MANUAL.

I'm curious whether the video channel can be running without any interruptions from the data channel. (i.e, no degrading in video throughput)
It would be great for me if the data and video can be exchanged irrestective of each other.

Any idea or suggestions will be highly appreciated.

Regards,
Rossi

Hi,

I got the green color streaming from OH01A10, like in the below thread.

https://community.infineon.com/t5/USB-low-full-high-speed/Streaming-Raw10-data-OV7251/td-p/105107

I going to do, convert RAW10 to RGB demosaicing using Opencv Library.But I cannot decode OpenCV's output, "YUY2 frame." 

I'm trying to print the frame shape in Python-, with three planes for each pixel, like (print(frame.shape) ->640, 480, 3).

I don`t know,  how I do to convert the "YUY2 frame – 3 Plane"  to "Single-Plane RAW10 Bayer"

CX3 Sensor Config:

I am trying to diagnose timing problems on my device using the Slave FIFO example as a starting point and had 2 clarification questions. The questions are the following:

1. Is it ok to de-assert SLCS as the FIFO address changes? Currently I am de-asserting SLCS when the address on GPIF changes and then reasserting to continue writing.

2. For the Data IN lines is the High Z state required? Currently I am leaving the data lines in an "I Dont Care", "0" or "1" state and am wondering if that is ok.

Thanks,

I have a need to write synchronously to a DAC. No samples can be skipped. This requires multiple threads ping-ponging, just as it does on reading. However...

According to https://community.cypress.com/t5/USB-Superspeed-Peripherals/GPFI-II-question/m-p/84212 there is a bug in GPIF Designer which requires an extra state to be inserted between driving on thread0 and driving on thread1. Without this extra state, GPIF Designer reports:

"'Thread Number' in action 'DR_DATA' of state-'WRITE_TH1' need to be same as 'Thread number' of action 'DR_DATA0' in state 'WRITE_TH0'"

This extra state causes the GPIF to not write a sample every DMA buffer, which is a huge problem.

So, questions:

1) Is this a bug in GPIF Designer or in the GPIF state machine? If the former, can we get a fix? That bug was pointed out more than 6 years ago and prevents synchronous continuous write from working at all. If the latter, is there a workaround?

2) Is there documentation available about the waveform states (alpha, beta, lambda) so I can work around the GPIF Designer bug and write my own state machine? I've tried reverse engineering the bits, but don't want to burn days investigating something which may never work.

I've attached two images--the first is the state machine I want, but GPIF Designer will not let me have. The second is the state machine I can get, but does not work due to the skipped GPIF driving samples.

Thanks for the help!

Hi,

After bootloder finishes successfully via Cypress USB Control Center, I have to do a power cycle to run the code.

The PMODE[2:0] is Z1Z, I2C ->USB

This the post build step:     elf2img.exe -i ${ProjName}.elf -o ${ProjName}.img -v -i2cconf 0x2C

Since I am not using 2-stage bootloader then:   #define CY_U3P_SYS_MEM_TOP (0x40080000)

I write 0xA5 to the first address of the EEPROM then I reset the MCU, Cypress USB Control Center detects the bootloader. Then by suing this tool I update the EEPROM and it says successfully, but it doesn't leave the bootloader.

I can see the bootloader is transmitting over UART:

▒▒=1C: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=1D: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=1E: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=1F: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=20: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=21: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=22: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=23: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=24: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=25: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=26: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=27: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=28: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=29: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=2A: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=2B: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52
▒▒=2C: Device initialized. Firmware ID: 50 33 58 46 0 47 4F 52

Even if using the "Reset Device" button in the Control Center doesn't reset the device.

Thanks 

I have been working on debugging DMA errors with the FX3 connected to a Xilinx FPGA and using the FX3's built-in FIFO to transmit UVC data between the two devices. In the process of changing the FPGA's source to only transmit when a full video frame is available I have encountered a strange state where when I configure the FPGA to produce some dummy data for the FX3, enable PCLK transmission on the FPGA side and then open up the FX3 in the Windows Camera app I can see multiple small packets of UVC data being transmitted on UART logs and Wireshark but I see no activity on the control lines in an ILA capture. I have included an ILA capture, Wireshark capture, and UART logs from when this state is encountered. I have also included the firmware image and FX3 source which allow this state to be entered. Below I recap the exact steps taken. Any help figuring out how these buffers are being generated when there is no controls active would be greatly appreciated.

1. Upload firmware to FX3, reboot device
2. Enable video input and PCLK from FPGA and open up UART logs
3. Unplug and re-plug FX3 USB cable into laptop
4. Start Wireshark capture
5. Open Windows Camera app and open the FX3 UVC camera
=== "UVC Buffer: XX bytes" messages start flooding UART logs ===
6. Take ILA capture
7. Close UART log
8. Stop Wireshark capture

Thanks,

Hello everyone,

I am trying to modify the example of "Application Notes 65974 Rev. P"  that shows how to design an interface between FPGA and FX3 using 32 bits Slave Synchronous, described on Section 11.2 and 11.3.

I would like to use 8 bits data width instead of 16 or 32 bits as described in the example, using Stream - IN transfers Read/Write between Host PC, FX3 and FPGA.

I modified the Interface via GPIF Designer to have 8 bits data bus, 2 address pins lines and 2 flags (A and B).

Then I got confused because Section 9.2 shows the same idea using 16 bits with 2 flags using partial watermark flags. Where is the source code for the FW and GPIF projects (section 9.2)?

Thanks in advance.

Rgrds

Marcos

Hi everyone,

I am presently trying to build an application that reads in a series of bytes over USB and then clocks them out 2 bytes at a time over the GPIF interface. I have modified the GPIFtoUSB example by changing the DMA config to have a USB socket as the producer and a GPIF socket as a consumer:

	CyU3PMemSet((uint8_t *) &dmaCfg, 0, sizeof(dmaCfg)); // Initialize all values to 0.
	dmaCfg.size = CY_FX_DMA_BUF_SIZE;
	dmaCfg.count = CY_FX_DMA_BUF_COUNT;
	dmaCfg.prodSckId = CY_FX_EP_PRODUCER_SOCKET;
	dmaCfg.consSckId = CY_FX_GPIF_CONSUMER_SOCKET;
	dmaCfg.dmaMode = CY_U3P_DMA_MODE_BYTE;
	dmaCfg.notification = 0;
	dmaCfg.cb = 0;
	dmaCfg.prodHeader = 0;
	dmaCfg.prodFooter = 0;
	dmaCfg.consHeader = 0;
	dmaCfg.prodAvailCount = 0;

The sockets are defined as follows:

#define CY_FX_EP_PRODUCER          0x01                     /* EP 1 Out */
#define CY_FX_EP_PRODUCER_SOCKET   CY_U3P_UIB_SOCKET_PROD_1 /* U-Port Output socket 0 */
#define CY_FX_GPIF_CONSUMER_SOCKET CY_U3P_PIB_SOCKET_0      /* P-Port Socket 0 */

 I then created a simple state machine:

The idea was that the machine would sit in DMA_WAIT until some data was available in the DMA, then clock that data out using DR_DATA. It will repeat DR_DATA until the DMA buffer is empty, at which point DMA_RDY_TH0 would deassert and the machine would go back to DMA_WAIT. The DR_GPIO is just set to toggle so that I have an idea when transitions are happening (or when WRITE_TO_GPIF cycles multiple times.

However, when I write some data to the FX3 using the USB control center, nothing happens. I can write 128 bytes to the FX3, at which point it times out so data seems to just pile up in memory.

I'm thinking this might have something to do with which thread DR_DATA is looking at? How do I know which thread the USB interface will use to toggle DMA_RDY?

Much appreciated!

Hi I am generating pwm duty cycle with cx3 chip 
previously i used complexupdate api it has some proble its not reflecting the values 
Then i accessed register for updating the threshold value every time i changed the duty cycle the problem is when duty cycle changed to 100 perc its reflecting in dso as 50 percent can any one have idea on it  

Thanks in advance

Best Regards

Clinton

Hi, I am using CYUSB3014 to stream live images to the PC using a bulk endpoint. I get error 997 for WaitForXfer , FinishDataXfer. Also I get USB underrun error in the firmware. 

I am using DMA in manual many to one having two GPIF as the producers and one USB  (CY_U3P_UIB_SOCKET_CONS_1) as the consumer. There are two buffers per sockets. When there are some errors I like to reset the whole stream of the data. The code I return resets the GPIF using CyU3PGpifSMSwitch to go to start state then I run the followings:

1. CyU3PDmaMultiChannelAbort
2. CyU3PUsbFlushEp
3. CyU3PDmaMultiChannelReset
4. CyU3PDmaMultiChannelSetXfer
5. CyU3PGpifControlSWInput, I use this to resume the GPIF to generate the data and starts to commit them.

The thing is when I run the above I can see the call back for the DMA is being called four times saying there consumer event. I am wondering why when I run the above the call back for the DMA is being called four times.

Thanks 

Behzad