USB superspeed peripherals Forum Discussions
I want to choose cyusb3.0 emmc to make a customer udisk solution.
But I can't find any detail information from datasheet.
Can cypress send me one?
Show LessHello,
I asked for help a few days ago about "Configuring an FPGA via FX3 CYUSB3014". But it wasn't full answer. And my research was going on.
I found out that a FPGA (Artix-7 in my case) and a SPI Flash can not be programmed using only FX3 controller. It is imperative to use a serial-to-USB converter to connect to the standard FPGA chain. The version that is available in the manual "AN84868 Configuring an FPGA Over USB Using Cypress FX3" works only for configure an FPGA in the slave serial Configuration mode and debugging FPGA through USB. But not for flashing the ROM. There is a method, but I do not want to use it, because it describes a little (XAPP1188; "FPGA Configuration from SPI Flash Memory using a Microprocessor") Unfortunately.
I decided to connect a serial-to-USB converter like a FT2232 to JTAG chain and use a separate data stream USB 3.0 and a FPGA-SPI Flash configuration separately. It'll be the easiest variant.
My new question is:
Is it possible to connect USB 2.0 and USB 3.0 with different controllers to a same connector? Should I break the line of communication USB 2.0 signals (DN, DP) from the controller FX3 to the USB 3.0 connector to connect to this place the FTDI USB 2.0 controller signals?
Show LessHello,
mine design progresses and the next challenge is the correct understanding of supply to the chip supply CYUSB3014. The Kit EZ-USB FX3 powered by USB bus or external power supply, such as the Spartan S601 Kit. My design has its own supply chain, all the necessary 5 V, 3.3 and 1.2 volts. In datasheet "EZ-USB FX3 Technical Reference Manual" on page 94 says: "1. Wait for a valid VBus voltage" and "Any PHYs that are enabled need to be disabled when the VBus voltage is removed. The entire previous procedure needs to be repeated when valid VBus is detected again" and "Note that USB 3.0 PHY on the FX3 needs to be turned off when VBus is removed or a host disconnect is discovered by other means. If the 3.0 PHY is left turned on, the 3.0 link startup is liable to fail when connected again to the host." What correctly is that mean? Can I supply only pin VBUS or VBATT (or both) from USB bus to comply with these requirements disable PHY when the device is not connected to USB, but other voltages (VIO[1..5], CVDDQ, VDD, AVDD, U3TXVDDQ/U3RXVDDQ) take from my power chain all time without interruption? Or I must take all voltages from VBUS by means of LDOs like in EZ-USB FX3 reference schematic?
Show LessTwo questions on the use of EPSWITCH to switch between physical sockets in 5-bit slave FIFO mode:
1) AN68829 timing diagrams show SLCS# low during EPSWITCH# assertion, yet KBA90268 says SLCS should be high. One of these is in error, probably KBA90268, correct?
2) AN68829 states that when asserting EPSWITCH# to wait until FLAGA (DMA_READY) becomes 1, indicating data is available, before deasserting EPSWITCH#. But what about the (likely) case where we're switching to a Read-from-FX3 socket that doesn't have any data available in it? In that case FLAGA is low (empty) and will stay low. We can't get stuck waiting for data here while other sockets need handling. If we implement a timeout (how long?) to exit an incomplete EPSWITCH, what state (which physical socket) are we leaving that thread in? Did it successfully switch to the new physical socket even though flagA never deasserted?
Show LessRelated thread:
http://www.cypress.com/forum/usb-30-super-speed/how-setting-fx3-full-speed
I would like to reduce the data rate of EZUSB FX3 down to 12 Mbps and application software is constructed on CYUSB.dll for .NET.
I tried to force FX3 to full speed or 12 Mbps mode, and I added CyU3PUsbForceFullSpeed(CyTrue) to the example 'cyfxbulkstream' or 'USBBulkStreams', along with the related thread above. The source code now looks like below:
/* This function initializes the USB Module, sets the enumeration descriptors. * This function does not start the bulk streaming and this is done only when * SET_CONF event is received. */ void CyFxBulkStreamsApplnInit (void) { CyU3PReturnStatus_t apiRetStatus = CY_U3P_SUCCESS; ... apiRetStatus = CyU3PUsbForceFullSpeed(CyTrue); if (apiRetStatus != CY_U3P_SUCCESS) { CyU3PGpioSetValue(54, CyFalse); } /* Connect the USB Pins with super speed operation enabled. */ //apiRetStatus = CyU3PConnectState(CyTrue, CyTrue); apiRetStatus = CyU3PConnectState(CyTrue, CyFalse); if (apiRetStatus != CY_U3P_SUCCESS) { CyU3PDebugPrint (4, "USB Connect failed, Error code = %d\n", apiRetStatus); CyFxAppErrorHandler(apiRetStatus); } }
I tried to check the full-speed-only firmware on C# Blukloop and C++ Streamer which were accompanied with EZUSB FX3 SDK. C# one does not recognize the full-speed-only device, C++ one looks to see it as shown in the two attached screen captures. I could see the full-speed-only device on Windows Device Manager. I also tried to watch the device from CYUSB.dll .NET with C#, but it did not recognize the full speed only device. The firmware was downloaded with Cypress Control Center, which did not recognize the full speed only device after downloading. Version of Windows is also attached. I use version 1.3.3 of EZUSB FX3 SDK.
Show LessHello,
I am java programmer and I have CYUSB3KIT EZ-USB fx3
I want to ask if there is any java library that provide my USB device ?
Or, if there is any way to use current library in Java ??
Thanks
Show LessHi, We have a CX3, which is operating a Sony CMOS imager and utilising the MIPI data bus. We find that the MIPI reset pad is driven high at start-up and remains that way - apparently preventing MIPI transfers. The pad has a 10K pull-down but is otherwise unconnected. Is the MIPI reset somehow configured as an output, rather than an input? We cannot find any reference to setting its state in the data sheet.
Regards,
Terry
Show LessHello,
I need help in getting start with the USB 3.0 FX3 Controller (CYUSB3014-BZXI). Information about the Kit EZ-USB® FX3™ tells that I can connect the Kit board to my development PC using a SuperSpeed port for load the firmware into FX3 RAM (Getting Started with EZ-USB® FX3™, page 20). Picture on page 21 shows that I can configure I2C EEPROM and SPI FLASH same method. Is that enough to use the FX3 controller in the SyncSlaveFIFO interface with the FPGA and configure the FPGA Artix-7 from the USB 3.0 connector?
My doubts lie in the fact that the schematic and the other documentations on this Kit contain a micro-B USB connector on the same Kit board "for Integrated Debugger". I dont know yet what is that mean, but affraid that I cant load the firmware into the CYUSB3014-BZXI and so cant use my design in the SyncSlaveFIFO interface with the FPGA in 16 bit mode without using additional USB-Serial bridge controller CY7C65215 and additional micro-B USB connector.
Or I should not have worried? And this micro-B USB is surplus for additional debug during operation?
Additionally, if I can use only a connector USB 3.0 to configure the FX3 controller and I2C EEPROM with "Cypress EZ USB Suite" for further download only from the I2C EEPROM without USB 3.0 connection?
Show LessHello,
I'm currently working with the SuperSpeed Explorer Kit (CYUSB3KIT-003) to communicate with an FPGA ( type Altera Cyclone IV ). I have programmed it with the bulkloop example to send to and get Data from the FPGA.
The problem is I'm getting inaccurate Data when clicking on the Transfer Data-OUT and I do believe it is because of a GPIO pin that alternates randomly between 0 and 1.
The question is can I change the pin assignment of the SuperSpeed Explorer Kit to solve my problem ?
Thanks
Show LessHi,
(A)
I am trying to setup the Stream-in-case of AN65974(the EZ-USB FX3 Slave FIFO Interface)
by using "EZ-USB FX3 SuperSpeed Explorer Kit".
The softwares (SDK 1.33 and Explorer Kit) are installed successfully.
(B)
Here are configurations:
Loaded Firmware: AN65974-SF_streamIN.img
PC Application: SDK1.3/application/c_sharp/streamer/bin/Release/Streamer.exe
EZ-USB FX3 Pin:
CTL0(GPIO[17] or SLCS#) = GND
CTL1(GPIO[18] or SLWR#) = GND
CTL2(GPIO[19] or SLOE#) = 3.3V
CTL3(GPIO[20] or SLRD#) = 3.3V
CTL4(GPIO[21] or FLAGA) = Floating
CTL5(GPIO[22] or FLAGB) = Floating
CTL6(GPIO[23] or FLAGC) = Floating
CTL7(GPIO[24] or PKTEND#) = 3.3V
CTL8(GPIO[25] or FLAGD) = Floating
CTL11(GPIO[28] or A1) = GND
CTL12(GPIO[29] or A0) = GND
PCLK(GPIO[16]) = accurate 8.192 MHZ clock(50% duty cycle)
DQ[0:31] = GND or 3.3V
I cannot find the mapping for CTLX and GPIO[XX] in the docs temporarily,
so the above mapping is according to the PCLK = GPIO[16] and PCB labeling.
And then the PC application Streamer.exe can start and run the stream-in mode.
If the above mapping is wrong, please inform me.
(C)
My question is:
The physical PC stream-in-Throughput(32500 KB/s shown in Streamer.exe) is wrong(not enough)!
The Throughput should be 32768 KBytes/Sec(8.192 MHZ * 32bits = 32768 KBytes/Sec)
I tried to increase the "Packets per Xfer" and "Xfers to Queues", but the results are the same
after running Streamer.exe for a long time.
I did not change the source code or firmware, but just setup AN65974-streamIN mode according to the above pin mapping.
Do you have any idea? Your any help will be much appreciated!!
BR,
cykuo