USB superspeed peripherals Forum Discussions

Hi, everyone:

     I get a problem with FX3 GPIF port.

     According to my understanding，a P to U DMA manual Channel will commit data to Host in follow two conditions:

     1. one buffer filled

     2. PKTEND became low

     In my test, I control the PKTEND in FPGA, and the last data packet is not  equal to the buffer size , sometime HOST can receive the last packet, but sometime can not, until the buffer size that include the last packet filled with the next fram data packet. I am sure the FPGA prroutine  is fine, it seems like the FX3 didn't respond the PKTEND.

     Are there any suggestions? Or are there any other way to control the condition that commit data?

Hello

We are understanding that the operating frequencies supported are 400 kHz and 1 MHz when VIO5 is 1.8 V, but the customer said that they want to use I2C bit rate as 100kHz when VIO5 is 1.8V.

Is it possible or not?

Best regards

Arai

Hi！

CyU3PDmaChannelConfig_t    CyU3PDmaMultiChannelConfig_t  each have parameters size。

CyU3PDmaChannelConfig_t    AA;

AA.size =1024;

AA.count = 8;

CyU3PDmaMultiChannelConfig_t BB;

BB.size =1024;

BB.count = 8;

In the AA,the DMA total size is 1024*8  and each buffer size is 1024.

In the BB,the DMA total size is 1024     and each buffer size is 1024/8=128.

Whether I understand correctly or not？

Hi all,

I have one problem in 32 bit GPIF. I am using FX3 in 32 bit GPIF mode. Since I was used 32 bit GPIF I can't use the default uart line (GPIO 48) for transmit the data. So I used SPI line (MISO line (GPIO 55)) as uart TX. For my application, I need to set SPI line (uarrt tx) initially as Pull UP (high). So I configured this by using CyU3PDeviceGpioOverride() function. But after sometime I need to use this GPIO as UART TX. Is there any possible ways to do this?.  I tried one way, Initially I configured the UART Tx (GPIO 55) as GPIO by using CyU3PDeviceGpioOverride() function and after sometime I disable that GPIO using CyU3PGpioDisable(). But it was not waorking. if any knows the answer please reply this question. Thanks in advance

Hi,

no matter what I do I get a red badge (error/warning) next to Output Pixel Clock in the " CX3 MIPI Receiver configuration" tool.

The currently calculated value is 127.20MHz

The min value is 110.88, The max value is 100. The max value is smaller than the min!

Could you please provide guidance how the min&max can be influenced?

Hello,

I'm trying to create an application which starts a SPI DMA transfer of 200 bytes every time there is a positive edge on one of the GPIO pins. Right now, I am polling the pin using CyU3PGpioGetValue and starting the DMA transfer on the positive edge by calling CyU3PSpiSetBlockXfer. However, this does not provide the speed that I need for my application, and the RTOS thread manager interrupting the execution of my application thread occasionally causes the application to miss the edge. I tried configuring a GPIO interrupt handler using the Api provided in cyu3gpio.h, but was unable to get CyU3PSpiSetBlockXfer to run inside of the ISR, as it seems like some API calls cannot be called within an interrupt handler. Is there any way to directly set the DMA controller to read SPI data in on an interrupt, or to allow for running a SPI transfer inside an ISR?

Thank you for any insight.

I have the CX3 device on a Denebola board and I'm trying to make a Sony IMX219 work.

I got it working in VGA with this configuration:

CyU3PMipicsiCfg_t cfgUvcVga30NoMclk =  {

     CY_U3P_CSI_DF_RAW10,        /* dataFormat   */

     2,                            /* numDataLanes */

     1,                          /* pllPrd       */

     63,                            /* pllFbd       */

     CY_U3P_CSI_PLL_FRS_500_1000M,   /* pllFrs      */

     CY_U3P_CSI_PLL_CLK_DIV_8,      /* csiRxClkDiv  */

     CY_U3P_CSI_PLL_CLK_DIV_8,      /* parClkDiv    */

     0x00,                          /* mclkCtl      */

     CY_U3P_CSI_PLL_CLK_DIV_8,      /* mClkRefDiv   */

     640,                          /* hResolution  */

     0x0A                          /* fifoDelay    */

};

The only "problem" is that it only works when Probe and UVC are configured for 640x482, instead of 640x480, and it sends 2 black lines to host PC, but I can deal with that.

The GPIF bus is 16 bits, and the camera clock has been increased to the maximum value possible that makes it work.

With this configuration, I can easily receive ~110 fps.

Since it works with different camera clocks configurations, but the same MIPI block parameters, I guessed that the MIPI configuration shown above should work for every other resolution. After all, if I don't modify the camera clocks, the bit rate will be the same, and the CX3 MIPI block wouldn't have a problem reading it.

Therefore I changed the camera configuration to work in 720p, with the same clock configuration. And it is not working.

What do I need to change? Why do I need to change something?

I have a byte count to see how many bytes does the DMA send to the USB, and I am getting 0x1CC0E8, when I should be getting 0x1C2000.

Reading in the community, I found that CX3 firmware must be modified to work with MIPI continuous clock. Below are my MIPI signals: yellow is the clock and blue is data lane 0. Is this clock continuous?

I tried doing this when a SET_CUR request arrives from host:

status = CyU3PMipicsiReset(CY_U3P_CSI_HARD_RST);

status =  CyU3PMipicsiInit();

status = CyU3PMipicsiSetIntfParams (&cfgUvc720p60NoMclk, CyFalse);

/* Sensor configuration */

As explained in the FAQs. But the result is still the same. Am I doing this wrong? Do I have to do this?

Hello everyone,

I am a beingger of FX3

I try sample code "GPIFtoUSB" of SDK

The project would catch GPIF one time when power on and transmit by endpoint 0x81

But GPIF always keeps first state

Question is: how to update state of GPIF continually?

Thanks