USB superspeed peripherals Forum Discussions
FX3 is connected to FPGA as below, run the FPGA program and reset FX3, FX3 USB bootloader device can't be shown in Control Center. When disconnect all pins between FX3 and FPGA, reset FX3, FX3 USB bootloader device can be shown in Control Center.
Similarly, separate FX3 and FPGA, burn firmware into FX3. Run the FPGA program and reset FX3, firmware can't be run. Can the output signals of FPGA affect the boot up sequence of FX3? Please kindly advise.
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Hi,
Add start state RD_START and GPIF II compile passed.
Change SRAM_READ_COMMAND, CyU3PGpifSMWitch toState to 'RD_START'.
Why tool still reports 'RD_START' can't be resolved?
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We are trying to use the APIs CyU3PGpifWriteDataWords/CyU3PGpifReadDataWords using the FX3 as master and an FPGA as slave. The objective is to be able to write/read registers in the FPGA.
Note that the GPIF is set up for 32-bit synchronous with multiplexed data and address.
A simple example along with a minimal GPIF2 project would be very helpful. None of the examples in SDK 1.2.2 illustrate the use of the two APIs mentioned above.
Any help would be highly appreciated.
Hi,
By referencing SRAMMaster example, I've created a simple register read/write project.
Please note, I've swapped write initial state name (START) with read initial state (RD_START), since don't know how to start the read flow.
Like the example, I'm using AddressCounter as address source.
It's "working", but start address is tied to 0.
How can I set start address to any 32 bits value?
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Hello,
I am working on a device that has two EEPROMS on the I2C bus. Unfortunately, the EEprom at the default 0xA0 address is not large enough to hold the image and we would like to boot from the device that is addressed as 0xA8 (write). Is there any way to configure FX3 to boot from this?
I have thought of using the example bootloader code, and changing it to read from the EEPROM with address 0xA8 and then loading this into the EEPROM at 0xA0 (that is too small for the actual image, assuming it will fit.) Then I would load the actual image where we want it and am wondering if this would be a valid setup. So I would picture the device powering up, and booting from the small eeprom at 0xA0 and that bootloader then goes out and boots from the eeprom at 0xA8 that has the actual code and then boots that code. Is this correct/possible behavior? Is there an easier way?
Thanks for your help,
Kevin
Show LessHi all,
I am building a USB device which needs to consume as less power as possible.
I was using Fx3s with SPI-Flash to boot the device, and the typical SPI-flash read current is about 10mA, while the F-RAM needs only 10 times less current.
Would it help to reduce the overall power consumption?
As there would be a 8-Mbits F-RAM coming, Is it possible to use it as the booting flash for Fx3S?
Thanks,
Jay
Show LessIn AN84868, IO matrix configuration are different in configuration phase and slave FIFO transferring phase. The corresponding GPIFII DESIGNER project seems to only match slave fifo io configuration. However, The main firmware project uses 32 bits slave fifo operation and GPIFII DESIGNER project uses 16 bits configuration. Why the two projects do not match with each other? Should GPIFII Designer project have two different configurations corresponding to FPGA configuration and SLAVE FIFO transferring?
Thank you.
Show LessHi,
SRAMMaster example GPIF II project has a separate start state START1 and compile passed.
Add the same START1 to my project. Why tool reports error?
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Hello sir ,
i have to generate a clock out pulse on fx3 pin using pwm of frequency 24 MHZ with 50% duty cycle for camera module ,also i have merged complexgpio example firmware with uvc .my question is in that complexgpio example they have set period as (201600 - 1) and threshold as (50400 - 1). unable to understand how these values are taken.please help.
Thanks
Manisha
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