USB superspeed peripherals Forum Discussions
The FX3 SDK for Linux v 1.3.3 includes the example 07_bulkreader.c in which the API uses libusb_bulk_transfer (trivially wrapped) to receive 64 bytes from the device.
r = cyusb_bulk_transfer(h1, 0x83, buf, 64, &transferred, timeout * 1000);
Here a request is being made to fill buf with at most 64 bytes.
The documentation for libusb states that to avoid an overflow situation, the buffer and max length provided should be a multiple of the wMaxPacketSize attribute of the endpoint to avoid an overflow where the device returns more data than libusb can handle given the size of the buffer provided. Here, the right way to handle this according to libusb, is to make repeated calls to libusb_bulk_transfer with buffer size as a multiple of wMaxPacketSize. Unless the actual data returned is this wMaxPacketSize, the call will time out with the actual number of bytes transferred. A check needs to be made of the actual number of bytes returned and if this is less than expected, then the call has to be repeated until all the data has been read.
Not using a buffer that is a multiple of wMaxPacketSize, according to libusb, risks an overflow and this is something that I have seen.
lsusb reports that for the FX3 in our system, wMaxPacketSize is 1024 bytes.
Why doesn't the example included in the FX3 SDK use a multiple of wMaxPacketSize as recommended by libusb? Is this an oversight, or is this the right way and if it's the right way, then how can I avoid overlfows?
What is the right way to make a bulk read of a lot of data that avoids the risk of overflow?
Show LessHello,
I'm using FX3 to communicate with FPGA with a PCLK signal generated by FPGA side. In the past, our product is working fine with PCLK = 74.25MHz, and now we are trying to speed up the PCLK to 100M. Without modification on the FX3 firmware, and directly increase PCLK frequency, we found following problem:
1. Total byte count is correct, but part of the packet data is shifted about 52 bytes latter(not fixed), event the packet is smaller than the DMA buffer size and WM is not related. But the last 32bytes of data are always correct.
2. Sending a packet larger than DMA buffer size, ready and WM stuck forever even PC side read data continuously.
We've checked the slack and time sequence on the FPGA side but found nothing. The output of FPGA data is not shifted. Is there anything I need to update for the change of PCLK?
Thanks,
W.D.
Show LessHi All,
I have modified the original project's firmware (found here: FX3 / CX3 Firmware for Streaming RAW Image Data using Cypress Driver to use the OV5647 sensor and am writing a simple PC app to receive and display the sensor data. I have questions about the use of the CyAPI functions.
After enumerating the USB bus and finding the Streamer Example Device, I am sending the vendor command 0x99 to start streaming. My target device receives and acknowledges the 99, but the PC side reports an error and says no data was sent. Also, what is the appropriate API call to receive the camera video data? I assume it is a dev.BulkInEndPt -> XferData( fbuf, fbufsiz ) transfer to alternating 16K buffers (or sensor frame sized buffers). Is that correct?
Any comments on what's happening are most appreciated.
Here's the code to send the vendor command:
BOOL send_vendor( CCyControlEndPoint *ept, BYTE cmd )
{
UCHAR buf[ 128 ], rbuf[ 128 ];
LONG buflen = sizeof( buf ), rbufsiz = sizeof( rbuf );
BOOL rls;
memset( buf, 0, buflen );
ept -> Target = TGT_DEVICE;
ept -> ReqType = REQ_VENDOR;
ept -> Direction = DIR_TO_DEVICE;
ept -> ReqCode = cmd; // vendor command
ept -> Value = 0;
ept -> Index = 0;
ept -> TimeOut = 300;
// rls = ept -> XferData( (UCHAR *) buf, (LONG &) buflen );
rls = ept -> Write( buf, buflen );
printf( "Vendor %02X, status %d, sent %d bytes\n", cmd, rls, buflen );
return( rls );
}
And the script of running the program:
There are 3 devices attached
Device 1, VID 4B4, PID 07: :USB-Serial (Dual Channel) Vendor 1
0 alternate interfaces
1 interfaces
Device 2, VID 4B4, PID 07: :USB-Serial (Dual Channel) Vendor MFG
0 alternate interfaces
1 interfaces
Device 3, VID 4B4, PID F1: SS:Cypress FX3 USB StreamerExample Device
0 alternate interfaces
1 interfaces
Opening Cypress FX3 USB StreamerExample Device
Bulk in endpoint
Vendor 99, status 0, sent 0 bytes
and the debug printout from the device:
bRType = 0x40, bRequest = 0x99, wValue = 0x0, wIndex = 0x0, wLength= 0x80Start streaming
AplnStrt:SMState = 0x2Stop streaming
AplnStop:SMState = 0x5Start streaming
This pattern continues to repeat.
Thanks,
Scott
Show LessI am working on a simple design that exposes the registers of an APB mapped peripheral located in a companion FPGA to FX3. My first instinct was to reconfigure the GPIF interface to generate native APB master to the FPGA. It seems like this would be a fairly common application, since many peripherals are available as AMBA compliant IPs. However, I can't seem to find any information or reference designs that do something similar. Is this problem already solved, or do I need to create some custom glue logic to connect the GPIF to an APB bus?
Show LessHi, i am currently able to capture frames from a toshiba csi-2 bridge. The data sent is in mono8, so the value are between 0-255 and represent a gray value. Is there any way to convert it to a rgb or yuy2 value so it can be streamed by uvc and played by any uvc viewer ?
ex. a value of 126 will be (126,126,126) in rgb. It can also be it any format as long that it recognized by uvc standard.
The image format is 320x240 at 30 fps. So an image is 320*240*8 = 76800 bytes. I guest that the data input should be in raw8 and the output in 24 bit, but then ? do i just need to change the guid in the usb descriptor ? If yes, how can i do that ?
Best regards
Thank you
Show LessHello,
I am trying to find the SPI speed of multiple transfers. I am currently using the SPI clk at 33MHz with a 32 bit transfer. This operates correctly but the delay between multiple SPI transfers seems to be much longer than the transfer speed.
1uS for transfer of packet using 32 bits.
delay of 14uS for transfer of next packet.
No delays between multiple transfers of packets just a loop of 10 32 bit transfers. I am seeing a long delay (14uS) after the first packet to the next packet from the SPI peripheral. We are currently using register transfers for the SPI.
1) What is the maximum speed of multiple transfers? back to back, 32 bit transfers out or in using SPI.
2) What are some options for reducing the transfer delay with the library calls?
3) Will using the DMA for SPI transfers reduce my delay between SPI packets?
Thank you,
Steve W.
Show LessHi,
We have some doubts about project that we are developing and we would like to know if the connection that we made between the Cypress CX3 and the USB 3.0 port is correct (see picture attached):
Best Regards,
Show LessHi all,
I have a question about the FX3 type-c Receptacle design below.
First, I want to get 5V / 3A via a USB C-type cable (Host: PC)
I know that the current that can be supplied according to the CC line is decided in the USB C-type application.
If I connect CC1 / CC2 with 5.1k pull-down as shown in figure 2 without separate CC controller, I want to check if there is no problem in receiving 3A.
With best regards
Ham
Show LessHI,
I'm using UVC+UART image file for FX3.
For Windows 10,it works fine for both UART communication and video streaming are working. In the device manager, I can see Imaging Device and COM Port.
For Windows 7, streaming is video streaming is fine but com port is detected in Device Manager. Please help if anyone has experienced a similar issue.
Show Less