USB superspeed peripherals Forum Discussions
Hi,
I have some problem about YUV upstream and UVC GET request.
The YUV 640x480@30 preview is ok when there is no UVC CONTROL request.
But if there is a UVC GET request on the USB HIGH SPEED connection,
YUV upstream is blocked and 'CyU3PDmaChannelCommitBuffer' throws error.
Is this some kind of bandwidth limitation? or bandwidth reservation for USB CONTROL endpoint?
Any advice and suggestions will be greatly appreciated.
Environment:
Sensor: Samsung M3085
Device : CX3 (512KB), SDK: 1.3.3 or 1.3.4
Preview : AmCap
Thanks in advance.
Show LessThe Raw10 monochrome will output as YUV format. May I know how does the Raw10 monochrome data split into YUV format, as my understanding Y=8bit, U=8bit and V=8bit. Total = 24bit. The Raw10 data is 10 bit, Y can only store 8 bit the remaining 2 bit will go into U or V?
Regards,
Nigel
Show Lessimport project “C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\dma_examples\cyfxbulklpmanual”, can not receive debug message in function CyFxBulkLpApplnInit(), I only change to another FW, host can receive debug message.
Show LessHello,
The code I'm using was taken directly from the synchronous slave fifo "cyfxslfifosync" example.
Besides the sync slave fifo protocol I need also to control GPIO bits from a control-transfer endpoint.
I found where/how to initialize the desired GPIO bits (done), but I have no clue how to add my code
to change GPIO bits from control endpoint.
I see the bulksrcsink example but I'm having difficulties to figure out how to integrate that with the
cyfxslfifosync code.
Please some hints, directions. Is there a more straightforward example for me to follow ?
Many thanks.
Luis C.
Show Less添付回路図のように基板を修正出来上がってきた基板でUSB BOOTで立ちあげて
Control Centerで書き込みをして、「Programming of SPI FLASH Succeeded」に確認して
基板をSPI BOOTにSWを変更して立ちあげても カメラの認識せず、USB BOOTLOADERで上がってきます。
SPIの状況を見ると、立ち上がり時にSPIの動作をしているのですが、少しで止まってしまっています。
デジアナでログを取りましたので添付します。
ROMを1個商社から聞いた実績のあるS25FS128SAに変えてみましたが状況は変わりません。
書き込んでいるイメージファイルを添付します。
以上、宜しくお願いします。
Show LessHi All,
Can someone point me to peripheral register view. Default superspeed sdk does not show anything in peripherals tab in debug view.
Interpreting through mem dump becomes quite difficult and time consuming.
Cheers
Rohith
Show LessI am using an FX3, still in the superspeed development kit. It is connected to an ADC and I can stream data from the ADC via the FX3 into a PC using GPIF_example 1 firmware, an all new state machine, and the CollectData PC Utility. To start the ADC, I did have to send out two 32 bit words to the ADC. These were coincidentally the same value, so I was able to load the data counter and then output this twice using DR_DATA with the correct timing within the GPIF II designer state machine.
However, this only allows me to use the ADC in its default mode, I actually need a different mode.
I now need to send more configuration words to the ADC. However, there only seems to be this one counter you can directly load in the GPIF II designer. How can I output other fixed words to configure the ADC before starting the streaming? I would appreciate a fully explicit answer, I am new to this. This may be related to the CY_U3P_PIB_GPIF_EGRESS_DATA(thread_number) macro to source data from registers or CyU3PGpifWriteDataWords() for sockets but can someone provide details of how these are used. How do I write data into these sources (presumably in the firmware) and then put them out on the data lines with GPIF II?
Show LessHi All,
I am successfully running an Omnivision OV5647 image sensor in 960p mode at 48.4 fps on the CX3 using Madhu's Streamer firmware project (FX3 / CX3 Firmware for Streaming RAW Image Data using Cypress Driver ) and a PC application I wrote using OpenCV. I am trying to slow the frame rate which seems to only be a matter of changing the imager's PLL multiplier register (0x3036) from 100 to 52 to produce about 25 fps.
When I do this and probe the sensor's MIPI stream I confirm its output frame rate has indeed dropped to 25.2 fps as expected. Using the CX3 configuration tool to generate new settings for the reduced frame rate doesn't change any of the settings that I was using at 48.4 fps. In fact, all of the settings in the CyU3PMipiCfg_t table for 960p remain the same, which makes sense to me since I expect the CX3's timing to be driven from the MIPI bus.
The problem I see is receiving the slower frame rate never transfers any images. Instead there is a constant stream of error 995 on the PC side. Can someone explain what I'm missing?
Thanks,
Scott
Show LessHello,
SPI interface (SPI_SCK,SPI_SSN,SPI_MISO,SPI_MOSI) in fx3 works only for booting(4 bit wire interface with spi flash).I cant use these (with another CHIPSELECT )spi controller for other slave (example zynq as slave controller).
if i do this interface,fx3 booting is going to fail.
what is the reason?
Thank you.
Show LessHi Sridhar,
I have just checked with onsemi, theAptina MT9m114 image sensor used in the AN75779 reference code is already in EOL. The latest MT9M114 eva board they have is using different interface, which mean there is no way to test out the AN75779 firmware whether can work with MT9M114. Please advise
The MT9M114 eva usd in AN75779:
https://www.ebay.com/itm/Aptina-MT9M114-55CSP-Demohead-Rev2-Board-CMOS-/283446418824
====Old Mt9m114 eva board====
The connection is similar with the Aptina interconnection board
This model already EOL
====New mt9m114 eva board======
The connection is diff with the Aptina interconnect board.
This model is still in production
Show Less