USB superspeed peripherals Forum Discussions
Hello. I am Lee.
I want to transmit the raw data of the RGB bayer image sensor using FX3.
For the first time, I made an FX3 test board and tested it.
The test board specifications are as follows:
1.1 FX3+ AP0101AT(onsemi ISP) + AR0132AT(onsemi Sensor)
1.2. Data bus: 8bit GPIF (I used cyfxgpif2config.h of UVC_AN75779 as it is.)
1.3. 1280* 960 @ 30hz, UVC(YUV422), 8bit
1.4. UVC Transfer (I used the example UVC_AN75779.)
Streamer @UVC data ( refer to 'FX3 / CX3 Firmware for Streaming RAW Image Data using Cypress Driver ')
toggled "#define CY_DRIVER" in uvc.h
1.5. The test board is working normally without any problems.
I attach this program. (The sensor initialization part is erased.)
And I am going to make a new board like this:
new board specifications :
2.1 FX3+ AR0132AT(onsemi Sensor): NO ISP
2.2. data bus: 12bit bus (16bit GPIF)
2.3 1280* 960 @ 30hz, RAW (RGB Bayer), 12bit
2.4 Only RGB bayer (Sterming mode and One shot mode)
I have a few questions.
Q1. What is the data size (RGB bayer) of 1 frame of the new board? Is 1280*960*2 byte correct?
Q2. Using the sensor's trigger mode (https://files.niemo.de/aptina_pdfs/TN_281_AR0132AT_TRIGGER_Mode_Operation.pdf)
I want to transmit only one frame and wait (one shot mode). What should I do in this case?
Q3. Is there any way to send a specific test pattern without sensor input?
For example, can a red screen be sent even if there is no sensor operation?
Q4. When changing to 8bit GPIF -> 16bit GPIF,
Can I change the data to 16 bits and change the LD_ADDR_COUNT and LD_DATA_COUNT values to 8183?
(LV, FV, PCLK function pins are the same.)
Are there any other modifications in the firmware or in the GPIF II Designer tool?
Q5. Cypress FX3 StramerExample Device @ USB control center
Streaming is turned on or off via 'Zero-length data CONTROL OUT' in the req code.
Could you ever send multiple bytes data pasted here?
ex) 0x99 0x12 0x34
If so, what should I process in firmware?
Q6. Cypress FX3 StramerExample Device @ USB control center
Can I receive whole 1 frame RAW data at once?
Sorry for so many questions.
I look forward to your help.
Show LessHi,
I am referring to FX3 Fail Safe Firmware Update , and able to implement the second stage boot loader for i2c and it is working as expected. same way I would like to use the second stage boot loader for SPI. How it can be achieved ? Do you have any reference design. So it would be very helpful.
Thanks in advance,
Best Regards,
Prasanna
Show LessMy project was compiled by mingw, but I have not been able to find the CyAPI.lib that can be used in mingw. Please refer to anyone who has encountered and solved this problem, thank you!
Show LessI'm trying to figure out some camera firmware that I inherited from somebody else. We're using a CX3 to control an Omnivision 4688. looking at the omnivision docs, it's got two PLL's with their own clock dividers and multipliers. The omnivision stuff has a SCLK_DEF, SCLK_OPT, a MIPI_PCLK, a MIPI_PHYS, a DAC_CLK, basically 5 clocks. When I go look at the CX3 documentation, it SEEMS like it has a couple PLLs along with associated clock multipliers and dividers as well. The CX3's clock params seem to go into cuy3mipicsi.c, and has values for the num of data lanes, the Prd, Fbd, pllFrs, csiRxClkDiv, and parClkDiv. The registers I send to the Omnivision 4688 have similar parameters passed to it for ITS PLL's!! What the heck?! How do I know which ones are the right ones to send!? Looking at the pinouts for the OV4688, there aren't many communication lines from/to the sensor chip and the CX3. It's unclear who is clocking who. Is the CX3 using the OV's pixel clock, or is the OV using the CX3's pixel clock? I'm not a firmware person, I'm a newbie. I don't understand who is generating the clock signals, and who is using the clock signals. Can somebody help explain?
Show LessWe just received our assemblies for our FX3-based board.
However, my operating system (as well as the USB Control Center) recognizes it as an SD3 instead of an FX3. I checked the package's silkscreen and it reads:
CYUSB3014-BZX
C 1931
A 33 THA
CYP 629235
Is it possible that I have an assembly problem?
An old IC fab?
A signal integrity design oversight?
I'm not sure how to proceed troubleshooting this. Any help is appreciated.
Show LessWe are using CYUSB3KIT-003 EZ-USB® FX3™ SuperSpeed Explorer Kit.
When we updated windows version, we encounter communication troubles
between the above product and our win PC. It seems that the problem depended
on a windows version. At the version of 1903 of win10, we encountered the above troubles
many times. When we updated to the 1909 version, we encountered the
above troubles but only in the case of a prolonged operating time. At the earlier
version than the 1903, however, the communication problem did not happen.
Could you let me know how to avoid the above communication problem?
Thanks in advance,
Tomo
Show LessIn my code, based on the cyfx3s_msc example, I would like to have up to 4 user data partitions.
The function arguments are commented (as below) that partCount should be less or equal to 4.
extern CyU3PReturnStatus_t
CyU3PSibPartitionStorage (
uint8_t portId, /**< Storage port to do the partitioning on. */
uint8_t partCount, /**< Total number of partitions required. Should be less than or equal to 4. */
uint32_t *partSizes_p, /**< Sizes for each of the first (N - 1) partitions. The remaining storage on the device will be assigned to the last partition. */
uint8_t *partType_p /**< Type for each partition (boot or data partition). */
);
My CyU3PSibPartitionStorage call returns CY_U3P_SUCCESS when I provide partCount 4, and four corresponding values for partSizes_p and partType_p.
Create partition idx: 0 port: 0 partCount: 4 partsize[0]: 1000000 parttype[0]: CY_U3P_SIB_LUN_DATA(0xDA)
Create partition idx: 1 port: 0 partCount: 4 partsize[1]: 1000000 parttype[1]: CY_U3P_SIB_LUN_DATA(0xDA)
Create partition idx: 2 port: 0 partCount: 4 partsize[2]: 1000000 parttype[2]: CY_U3P_SIB_LUN_DATA(0xDA)
Create partition idx: 3 port: 0 partCount: 4 partsize[3]: 1000000 parttype[3]: CY_U3P_SIB_LUN_DATA(0xDA)
CyU3PSibPartitionStorage port 0 Created 4 new partitions return code: 0
But when I reboot the device to use the new layout, there only exist two valid user partitions and two new invalid partitions which are marked as type CY_U3P_SIB_LUN_BOOT.
Found a device on port 0
... numUnits=6 ...
Dev 0, Unit 0: location=1 numBlocks=8192
Dev 0, Unit 1: location=2 numBlocks=8192
Dev 0, Unit 2: location=0 numBlocks=1000000
Dev 0, Unit 3: location=0 numBlocks=1000000
Dev 0, Unit 4: location=1 numBlocks=8192
Dev 0, Unit 5: location=2 numBlocks=8192
Digging deeper, I looked in the FX3 SDK source zip and the file sdk/firmware/src/storage/cyu3sib_fx3s.c:1301 there is a comment which reads:
/* This function partitions the user area of the card into two. */
CyU3PReturnStatus_t
CyU3PSibPartitionStorage (...)
So can the eMMC user area only be split in two partitions? The CyU3PSibPartitionStorage certainly accepts more and returns a successful result.
The JEDEC standard (image below) seems to indicate there are always the BOOT1 and BOOT2 partitions and that it should be possible to have four General Purpose Area partitions. It seems those aren't used and the CyU3PSibPartitionStorage call is just writing a custom Cypress-specific partition table to the eMMC flash itself, is that the case?
Is it possible to eliminate the BOOT1 and BOOT2 partitions? Is there any way to configure 2+ USER data partitions?
Thanks for any help, this is a critical issue for me at the moment.
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Hello,
The datasheet of the CYUSB306X rarely mentions USB-2 compatibility.
1) Can you confirm it is also compatible with USB-2 and not only USB-3?
2) What would be the frame rate, aspect ratio, size on USB-2?
Bests,
Mehdi
Show Less最近在CX3强化测试中发现,CX3在windows平台图像传输正常,同等测试条件,在Linux平台运行一段时间,时间不等, 会持续CX3会一直打印“DMA error”, linux接收端采用的是libusb,libusb_bulk_transfer 一直返回错误代码为-7,即LIBUSB_ERROR_TIMEOUT,图像端点不能上传,但控制端点正常,而重新插拨CX3,又能出图像。已经困惑很久,希望在此能收到点建议,谢谢。
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