Some settings in my design as follows:
DMA buffer: 16KB(size)X 2(number)
In my firmware:CyU3PGpifSocketConfigure (3,CY_U3P_PIB_SOCKET_3,6,CyFalse,1);
When fpga side transfer a short package(32B) to the host,the fisrt 4B data has losed，and the last 4B data was 00-00-00-00.The timing sequence as show in the picture named fpga.png.And the result of host recevied as show in the picture named host.png.The short package that fpga transfered is"0xcc88bb77 0xffff1007 0xffffffff 0xffffffff 0xabcdef01 0xabcdef01 0xabcdef01 0xabcdef01".And the data recevied by the host is" 0xffff1007 0xffffffff 0xffffffff 0xabcdef01 0xabcdef01 0xabcdef01 0xabcdef01 0x00000000".
what's wrong with the code?What is your advance?
1. Could you share your firmware project folder with us (including the GPIF project)?
2. Could you confirm if FX3 is receiving the data correctly?
I don't know how to confirm FX3 recevied the data correct or not ?I have no idea about how to locate the reason of the error.And I noticed that flagc and fladd worked bad when the error happened in the picture named fpga.png.By the way,the host sends a command frame(32B) to the fpga,and fpga recevied the command frame correctly than acknowledged an ack frame(32B) to the host side in my design. The error has happened in this process.
There is an accessory of my Firmware project .
Please try programming FX3 first and then FPGA. Kindly do try this and let us know if any errors?
I have not understood your mean.But there is a new solution about above-mentioned error.You know GPIF is a half-duplex,so only one operation on the bus at the same time.When fpga recevied commands from the host,the fpga code would delay some clks(100MHz) and then transfer short package as ack.If i set 15 clks(the time of delay) or 128 clks,there was an package loss(first 4B).But if i set 20 clks ，it work well.This why? And how to check the reason of those solution? Please reply as soon as possible.Thank you very much.
1. As only 32B are being transferred from GPIF to USB, try decreasing the DMA Buffer size and increasing the DMA Buffer count.
2. Try to send data only when flagC is asserted.
3. Could you send us the debug prints, printing the number of Prod and Cons Events?
1.32B are used for transfering commands from host.And in my application,after some necessary command frames and acks frame,the host will transfer a good deal of image datas by usb channel.
You know flagc and flagd would keep initial value when system initiation has completed ,and the initial value of flagc、d is set in the GPIF II Designer.And than,flagc will be low,and flagd will be high. If the host transfer 32B to fpga,flagc will be high,flagd will be high too.And if fpga has recevied 32B , buffer is empty now,flagc will be low .Flagd gets low is determined the value of the watervalue.And flagd will keep low until the buffer is not empty.Is that correct? If that is correct,flagc and flagd worked well all the time.
3.In my designed PCB, there is not a UART to print the number of Prod and Cons Events.
4.In order to exchange infomation between host and fpga,Fpga did read operation and write operation back to back.How long should be set between "read" and "write".In fact,if i set 20 clks(100Mhz) between "read" and "write",no any error.
Hi Jack Chen,
1. Increase the count of DMA buffers, even though the size is constant.
2. Your flags seem to work well.
After 32B is received from FX3, try writing to FX3 only when flagC goes low (denoting that the buffers are empty).