Oct 19, 2018
07:47 AM
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Oct 19, 2018
07:47 AM
Hi,
I've downloaded firmware reference design SlaveFifoSync, generated SF_shrt_ZLP.img.
Made below changes to FPGA example slaveFIFO2b_fpga (VHDL version) code, generated bit file.
1. Force mode to ZLP.
2. Tied flagc and flagd to gnd.
3. Add debug LED and probe signals.
I can program firmware.
Except one complete transfer, "Transfer Data-IN" always fail.
Noticed flagb is always low.
Checked pin location constraint is matching with schematic.
Why flagb is always low? How to fix this?
Thanks!
9 Replies