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USB Superspeed Peripherals

doch_3739346
Contributor

Hi,

I've downloaded firmware reference design SlaveFifoSync, generated SF_shrt_ZLP.img.

Made below changes to FPGA example slaveFIFO2b_fpga (VHDL version) code, generated bit file.

1. Force mode to ZLP.

2. Tied flagc and flagd to gnd.

3. Add debug LED and probe signals.

I can program firmware.

2018-10-19 12_26_04-hhgw28_2 (dgc) - TightVNC Viewer.png

Except one complete transfer, "Transfer Data-IN" always fail.

2018-10-19 12_57_04-USB Control Center.png

Noticed flagb is always low.

2018-10-19 14_51_20-hw_ila_1.png

Checked pin location constraint is matching with schematic.

pastedImage_7.png

pastedImage_8.png

pastedImage_9.png

Why flagb is always low? How to fix this?

Thanks!

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9 Replies
doch_3739346
Contributor

If I change FPGA code, tied flaga and flagb together, FX3 can receive data from FPGA.

pastedImage_0.png

pastedImage_1.png

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alamandaa_16
Moderator
Moderator

Hi,

-Please share the simulation wave-forms,when tied flag_a and flag_b together.

- Did you make any modifications to the application note firmware An65974? If yes, please mention the same.

- Can you please check  if the flagb was always zero from power on? If not, please provide the interface timing diagram before and after the flagb is going low.

- Did you make any modifications to the watermark value?

- Are you seeing any PIB underrun or overrun error when the flag status changed to low?

Regards,

Anil Srinivas.

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doch_3739346
Contributor

Hi Anil,

Currently I just run FPGA test.

Below is the waves captured with trigger fdata_d != 32'hFFFF_FFFF.

Not sure how to attach exported ila file.

pastedImage_1.png

Data in "USB Control Center" looks okay, not sure why fdata_d doesn't start with 0.

pastedImage_0.png

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doch_3739346
Contributor

Seems after power on, FX3 will receive the first packet with data started with 0.

But when I click capture in Xilinx Vivado, it's capturing second packet.

So after power on board, I need to hard reset FPGA and click "Transfer Data-IN", after this waves data are matching with "USB Control Center" data.

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doch_3739346
Contributor

Hi Anil,

1. I didn't change the SlaveFifoSync firmware.

2. Not sure how to check flagb from power on. Since it's an "internal" signal. The only way I can check flagb is through Xilinx Vivado probe. I can capture flagb signal before/after board hard reset. Please let me know if you need it.

3. Not sure about "watermark value", if it's related to why first data is not 0, I think I found the answer.

4. Not sure what's "PIB underrun or overrun error", I didn't notice any error/warning message from "USB Control Center".

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alamandaa_16
Moderator
Moderator

Hello Dong Chen,

-The Backflow(overrun & underrun error)error comes, when the DMA buffers get filled and the GPIF is still trying to write the data. If the host is reading the data slower than the data being written at the GPIF interface, then the DMA buffers will get filled and give this Backflow(overrun & underrun error).

Regard,

Anil Srinivas.

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doch_3739346
Contributor

Hi Anil,

Could you message your company email to me, it's not easy to attach file here.

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doch_3739346
Contributor

Hi Anil,

Thanks for the Backflow definition.

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alamandaa_16
Moderator
Moderator

Hello Dong Chen,

--Please provide the flagb signal timing diagram before/after board hard reset.

Regards,

Anil Srinivas.

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