I had read the DVK description as well as the AN76405. Both documents describe that the MISO and MOSI lines in SPI boot mode should not be connected to a pull up resistor. I do not know if it will work when I have connect those pins also to a FPGA I/O? Can anybody tell me a specifically description of the behaviour of MOSI and MISO lines.
You should be able to connect SPI lines to different slaves with out any issue. In your case, they are FPGA and SPI flash.
CS or SS (Slave Select) decides the device that FX3 wants to communicate.
Are you seeing any issue regarding this use case.
Please let me know.
It's critical to the boot process that there not be a pull-up on MISO. Some FPGAs have internal pull-ups, so you may need to add a strong pull-down in order to boot properly.
Clarification: floating MISO is not good either, if your boot flash tri-states that signal.
Hi Sai Krishna and Steve,
thanks a lot for your suggestions we have destined the additional pull down at MISO line in our hardware design.
You can enable the SPI block of FPGA once the firmware gets downloaded into FX3. You can use a GPIO as an interrupt to the FPGA to start the SPI module. In SPI disable mode, the lines should be kept floating,