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USB Superspeed Peripherals

schu_4025346
New Contributor

Currently, I use FX3 as a bridge for communication between a PC and an external FPGA board as shown below:

               read/write FPGA register request                  

PC      ---------------------------------------------->  FX3 ------------------------------------>  FPGA

               read FPGA data request                                   

In this design, FX3 GPIF is a synchronous master and used to:

1. read/write register space from/to FPGA;

2. read data space (FIFO) from  FPGA.

The two spaces of the FPGA are distinguished by an adress line of the GPIF interface, e.g. 1 for register space and 0 for data space.

on FX3 side, I tried to use three threads: the first thread (thread0) is used to read register value from the FPGA, the second one for writing FPGA register, and the thrid one for reading FPGA data, so I create three DMA channels as follows:

1.DMA1.prodSckId = 0x0102;      01: GPIF;        02: Thread 2;       //for reading FPGA registers

   DMA1.consSckId = 0x0302       03: USBOUT; 02: socket number 2 and mapped to end point IN 2;

2.DMA2.prodSckId = 0x0401;      04: USBIN;      01: socket number 1 ;   //for writing FPGA registers

   DMA2.consSckId = 0x0103       01: GPIF;        03: thread 3;

3.DMA3.prodSckId = 0x0100;      01: GPIF;        00: Thread 0;  //for reading FPGA data

   DMA1.consSckId = 0x0301       03: USBOUT; 01: socket number 1 and mapped to end point IN 1;

Now, the DMA2 and DMA3 can work well, that is, PC can sucessfully write register to FPGA and read data back from FPGA, but PC can not read FPGA register through DMA1 channel.

My question is that, if FX3 GPIF as a synchronous master, can more than one thread be used to transfer data from outside to FX3 engress end points? or there are any configuration errors in the DMA channel creation?

Your suggestions are very appreciated!

Scott

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13 Replies
alamandaa_16
Moderator
Moderator

Hi,

--Please share the GPIF project and code snippet of DMA channel creation.

Regards,

Anil Srinivas.

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schu_4025346
New Contributor

Hi Anil,

I have uploaded my GPIF project, please refer to the attachements(master_read_write_sync.cyfx, gpif2model.xml, gpif2timingsimulation.xml, and gpifview.xml).

The code snippet of DMA channel creation, please refer to the attached file AppInStart.c.

FX3 as USB slave, has one control point, one bulk out end point, bulk in end point 1 for reading FPGA sample value and bulk in end point 2 for reading FPGA register value.

Currently, from PC host, I can write FPGA register through FX3 and read FPGA sample value (data), but failed to read FPGA registers' value.

Thanks for your points in advance!

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schu_4025346
New Contributor

please refer to the attached GPIF project and the snippet code for DMA creation.

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schu_4025346
New Contributor

Hi Anil,

In the GPIF project, I tried to use Thread1/Thread2 to receive the FPGA register value, but both failed.

I am not sure that the mapping relationship between the end in point number on PC side and the socket number(or the thread number) on FX3 side is correct or not.

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alamandaa_16
Moderator
Moderator

Hi,

-----Please share the entire GPIF project file(.cydsn).

Regards,

Anil Srinivas.

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schu_4025346
New Contributor

hi,

Please refer to the attached file for the complete GPIF project.

Thanks!

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alamandaa_16
Moderator
Moderator

Hi,

You have created Two threads(thread0 and thread3) in GPIF statemachine so that the DMA2 and DMA3 can work well, that is, PC can sucessfully write register to FPGA and read data back from FPGA. you can create one more thread for reading FPGA registers.

Regards,

Anil Srinivas.

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schu_4025346
New Contributor

Hi,

Thanks for your response!

Yes, I have created one thread, e.g. thread 2 to read FPGA registers and the corresponding DMA channel as following:

DMA1.prodSckId = 0x0102;      01: GPIF;        02: Thread 2;       //for reading FPGA registers

DMA1.consSckId = 0x0302       03: USBOUT; 02: socket number 2 and mapped to end point IN 2;

unfortunately, in PC side, I failed to read the FPGA registers' value with end point IN 2.

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alamandaa_16
Moderator
Moderator

Hi,

Can you please provide the error messages. This will help us to spot the issue and give appropriate suggestions and please share the modified GPIF Statemachine.

Regards,

Anil Srinivas.

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schu_4025346
New Contributor

hi,

Please check the attached GPIFproject.

There is no error message while running the FX3 firmware. The problem is that PC application can not read the FPGA register value from end point 2.

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alamandaa_16
Moderator
Moderator

Hi Scott,

You have created two threads(Thread0 and Thread3) in above GPIF project.in your application you need 3 threads right.

please let me know, did you add Thread2 in GPIF project? and share the host application error messages.

Regards,

Anil Srinivas.

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schu_4025346
New Contributor

Hi,

We have changed the design now.

Only the GPIF interface is used to sample the value from FPGA. And a SPI bus is used to read/write registers' value from/to FPGA. By this changing, the problem has been solved. Thanks.

But we have another question, i.e, the latency from the action "IN_DATA" to the flag "DMA_RDY_THx" update? one GPIF clock, two GPIF clocks, etc.

We have checked the documents provided Cypress, but can not find the answer.

The attched file is updated GPIF project. In this project, FX3 acts the master, keeping reading the sample value from FPGA. FLAG_A indicates if there are data available on FPGA side. DMA_RDY_TH0 indicates if there is a free buffer on FX3 DMA channel.

If there are more than two GPIF clocks latency from last read operation (IN_DATA) to the DMA_RDY_TH0 updates, the state machine will not work correctly, i.e, the DMA buffer will be overflow.

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Rashi_Vatsa
Moderator
Moderator

Hello,

Please refer to AN65974 app note https://www.cypress.com/file/136056/download  to understand  about the DMA flags and their latencies.

Also, refer to this thread  does DMA_RDY_TH0 has latency? - Cypress Developer Community  

Regards,
Rashi
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